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WM8944BECS/R 数据表(PDF) 103 Page - Cirrus Logic

部件名 WM8944BECS/R
功能描述  Mono Low-Power CODEC with Video Buffer
PDF  165 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

WM8944BECS/R 数据表(HTML) 103 Page - Cirrus Logic

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WM8944B
Rev 4.3
103
REG
NAME
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DEFAULT
R26 (1Ah)
ADC Control 2
0
0
0
0
0
0
0
0
0
ADC_H
PF_MO
DE
ADC_HPF_SR
[1:0]
ADC_HPF_CUT [2:0]
ADC_H
PF
0021h
R27 (1Bh)
Left ADC Digital Vol
0
0
0
ADC_V
U
0
0
0
ADCL_
MUTE
ADCL_VOL [7:0]
00C0h
R28 (1Ch) Right ADC Digital Vol
0
0
0
ADC_V
U
0
0
0
ADCR_
MUTE
ADCR_VOL [7:0]
00C0h
R29 (1Dh) DRC Control 1
0
0
0
0
0
0
0
DRC_N
G_ENA
DRC_E
NA
0
0
0
1
DRC_
QR
DRC_A
NTI
CLIP
1
000Fh
R30 (1Eh)
DRC Control 2
0
0
0
DRC_NG_MINGAIN [3:0]
0
0
0
1
DRC_MINGAIN [2:0]
DRC_MAX
GAIN [1:0]
0C25h
R31 (1Fh)
DRC Control 3
0
0
0
0
0
0
1
1
DRC_ATK [3:0]
DRC_DCY [3:0]
0342h
R32 (20h)
DRC Control 4
0
0
0
DRC_KNEE2_IP [4:0]
DRC_KNEE_IP [5:0]
0
0
0000h
R33 (21h)
DRC Control 5
0
0
DRC_K
NEE2_
OP_EN
A
DRC_KNEE2_OP [4:0]
DRC_KNEE_OP [4:0]
DRC_HI_COMP [2:0]
0003h
R34 (22h)
DRC Control 6
0
0
0
0
0
0
0
0
0
0
0
0
DRC_QR_THR
[1:0]
DRC_QR_DCY
[1:0]
0000h
R35 (23h)
DRC Control 7
0
0
0
0
0
0
DRC_NG_ EXP
[1:0]
DRC_LO_COMP [2:0]
DRC_INIT [4:0]
0000h
R36 (24h)
DRC Status
(Read only)
DRC_GAIN [15:0]
0000h
R37 (25h)
Beep Control 1
0
0
0
0
0
0
0
0
0
BEEP_GAIN [3:0]
BEEP_RATE
[1:0]
BEEP_
ENA
0002h
R38 (26h)
Video Buffer
0
0
0
0
0
0
0
0
VB_EN
A
VB_QB
OOST
VB_GA
IN
VB_DISOFF [2:0]
VB_PD VB_CL
AMP
001Ch
R39 (27h)
Input ctrl
0
0
0
0
0
0
AUX_T
O_N_I
NPGA
0
0
MICB_
LVL
0
0
0
0
P_PGA_SEL
[1:0]
0001h
R40 (28h)
Input PGA gain ctrl
0
0
0
0
0
0
0
0
INPGA
_ZC
INPGA
_MUTE
INPGA_VOL [5:0]
0050h
R42 (2Ah)
Output ctrl
THERR
_ACT
0
SPKN_
VMID_
OP_EN
A
SPKP_
VMID_
OP_EN
A
0
LINE_V
MID_O
P_ENA
0
LINE_
MUTE
SPKN_
DISCH
SPKP_
DISCH
0
LINE_
DISCH
0
0
SPK_V
ROI
LINE_V
ROI
8100h
R43 (2Bh)
SPK mixer control1
0
0
0
0
0
AUX
DIFF_T
O_PGA
IN1_T
O_PGA
AUX_T
O_SPK
P
PGA_T
O_SPK
P
BYP_T
O_PGA
MDAC
_TO_P
GA
0
DAC_T
O_PGA
0
0
AUX_T
O_PGA
0000h
R44 (2Ch) SPK mixer control2
0
0
0
0
0
0
IN1_T
O_SPK
N
0
PGA_T
O_SPK
N
0
0
0
0
0
0
0
0000h
R45 (2Dh) SPK mixer control3
0
0
0
0
0
AUX
DIFF_T
O_PGA
_ATTE
N
IN1_T
O_PGA
_ATTE
N
AUX_T
O_SPK
P_ATT
EN
PGA_T
O_SPK
P_ATT
EN
BYP_T
O_PGA
_ATTE
N
0
0
DAC_T
O_PGA
_ATTE
N
0
0
AUX_T
O_PGA
_ATTE
N
0000h
R46 (2Eh)
SPK mixer control4
0
0
0
0
0
0
IN1_T
O_SPK
N_ATT
EN
0
PGA_T
O_SPK
N_ATT
EN
0
0
0
0
0
0
0
0000h
R47 (2Fh)
SPK volume ctrl
0
0
0
0
0
0
0
0
SPK_Z
C
SPK_P
GA_M
UTE
SPK_VOL [5:0]
0079h
R49 (31h)
Line mixer control 1
0
0
0
0
0
AUX
DIFF_T
O_OUT
IN1_T
O_OUT
0
0
BYP_T
O_OUT
MDAC
_TO_O
UT
0
DAC_T
O_OUT
0
0
AUX_T
O_OUT
0000h



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