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WM8944BECS/R 数据表(PDF) 107 Page - Cirrus Logic

部件名 WM8944BECS/R
功能描述  Mono Low-Power CODEC with Video Buffer
PDF  165 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

WM8944BECS/R 数据表(HTML) 107 Page - Cirrus Logic

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WM8944B
Rev 4.3
107
REGISTER BITS BY ADDRESS
The complete register map is shown below. The detailed description can be found in the relevant text of the device description.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R0 (00h)
Software
Reset/Chip
ID 1
15:0
SW_RESET
[15:0]
0110_0010
_0110_010
0
Writing to this register resets all registers to their default
state.
Reading from this register will indicate device family ID
6264h.
Register 00h Software Reset/Chip ID 1
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R1 (01h)
Chip ID 2
(Read only)
3:0
CHIP_REV [3:0]
0000
Reading from this register will indicate the Revision ID
(Read only).
Register 01h Chip ID 2
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R2 (02h)
Power
manage-ment
1
12
INPGA_ENA
0
Input PGA Enable
0 = Disabled
1 = Enabled
11
ADCR_ENA
0
Right ADC Enable
0 = Disabled
1 = Enabled
ADCR_ENA must be set to 1 when processing right
channel data from the Digital Microphone.
10
ADCL_ENA
0
Left ADC Enable
0 = Disabled
1 = Enabled
ADCL_ENA must be set to 1 when processing data from
the ADC or Digital Microphone.
7
DMIC_ENA
0
Enables Digital Microphone mode
0 = Audio DSP input is from ADC
1 = Audio DSP input is from digital microphone interface
When DMIC_ENA = 0, the Digital microphone clock
(DMICCLK) is held low.
5
SPK_
LOWVMID_
ENA
0
Selects 0.9V midrail voltage for speaker output drivers
0 = Disabled
1 = Enabled
This bit should be enabled if SPKVDD = 1.8V
4
MICB_ENA
0
Microphone Bias Enable
0 = Disabled
1 = Enabled
3
BIAS_ENA
0
Master Bias Enable
0 = Disabled
1 = Enabled
2
VMID_BUF_
ENA
0
VMID Buffer Enable.
(The buffered VMID may be applied to disabled input and
output pins.)
0 = Disabled
1 = Enabled
1:0
VMID_SEL [1:0]
00
VMID Divider Enable and Select



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