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WM8944BECS/R 数据表(PDF) 109 Page - Cirrus Logic |
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WM8944BECS/R 数据表(HTML) 109 Page - Cirrus Logic |
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109 / 165 page  WM8944B Rev 4.3 109 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO DAC_ENA must be set to 1 when processing data from the DAC or Digital Beep Generator. Register 03h Power management 2 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R4 (04h) Audio Interface 15:14 DACDATA_ PULL [1:0] 00 DACDAT pull-up / pull-down Enable 00 = no pull-up or pull-down 01 = pull-down 10 = pull-up 11 = reserved 13:12 FRAME_PULL [1:0] 00 LRCLK pull-up / pull-down Enable 00 = no pull-up or pull-down 01 = pull-down 10 = pull-up 11 = reserved 11:10 BCLK_PULL [1:0] 00 BCLK pull-up / pull-down Enable 00 = no pull-up or pull-down 01 = pull-down 10 = pull-up 11 = reserved 9 ADCR_SRC 1 Right Digital Audio interface source 0 = Left ADC data is output on right channel 1 = Right ADC data is output on right channel 8 ADCL_SRC 0 Left Digital Audio interface source 0 = Left ADC data is output on left channel 1 = Right ADC data is output on left channel 6 DAC_SRC 0 DAC Data Source Select 0 = DAC outputs left channel interface data 1 = DAC outputs right channel interface data 5 BCLK_INV 0 BCLK Invert 0 = BCLK not inverted 1 = BCLK inverted 4 LRCLK_INV 0 LRCLK Polarity / DSP Mode A-B select. Left and I2S modes – LRCLK polarity 0 = Not Inverted 1 = Inverted DSP Mode – Mode A-B select 0 = MSB is available on 2nd BCLK rising edge after LRCLK rising edge (mode A) 1 = MSB is available on 1st BCLK rising edge after LRCLK rising edge (mode B) 3:2 WL [1:0] 10 Digital Audio Interface Word Length 00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = 32 bits Note - see “Companding” for the selection of 8-bit mode. 1:0 FMT [1:0] 10 Digital Audio Interface Format 00 = Reserved |
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