WM8944BECSSLASHR datasheet(111/165 Pages) CIRRUS

111 / 165 page

WM8944B

Rev 4.3

111

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

SYSCLK_ENA

SYSCLK Enable

0 = Disabled

1 = Enabled

SYSCLK_SRC

SYSCLK Source Select

0 = MCLK

1 = FLL output

7:5

SYSCLK_DIV

[2:0]

000

SYSCLK Clock divider

(Sets the scaling for either the MCLK or FLL clock output,

depending on SYSCLK_SRC)

000 = divide by 1

001 = divide by 1.5

010 = divide by 2

011 = divide by 3

100 = divide by 4

101 = divide by 6

110 = divide by 8

111 = divide by 12

TOCLK_ENA

TOCLK Enabled

(Enables timeout clock for GPIO level detection)

0 = Disabled

1 = Enabled

3:1

BCLK_DIV [2:0]

011

BCLK Frequency (Master mode)

000 = SYSCLK

001 = SYSCLK / 2

010 = SYSCLK / 4

011 = SYSCLK / 8

100 = SYSCLK / 16

101 = SYSCLK / 32

110 = reserved

111 = reserved

MSTR

Digital Audio Interface Mode select

0 = Slave mode

1 = Master mode

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

.R7 (07h)

Additional

control

SYSCLK_

RATE

Selects the SYSCLK / fs ratio

0 = SYSCLK = 256 x fs

1 = SYSCLK = 512 x fs

VMID_FAST_

START

VMID (fast-start) Enable

0 = Disabled

1 = Enabled

VMID_REF_

SEL

VMID Source Select

0 = LDO supply (LDOVDD)

1 = LDO output (LDOVOUT)

VMID_CTRL

VMID Ratio control

Sets the ratio of VMID to the source selected by

VMID_REF_SEL

0 = 5/11

1 = 1/2

STARTUP_

Start-Up Bias Enable

WM8944BECS/R 数据表(PDF) 111 Page - Cirrus Logic

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WM8944BECS/R 数据表(PDF) 111 Page - Cirrus Logic

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