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WM8944BECS/R 数据表(PDF) 113 Page - Cirrus Logic

部件名 WM8944BECS/R
功能描述  Mono Low-Power CODEC with Video Buffer
PDF  165 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

WM8944BECS/R 数据表(HTML) 113 Page - Cirrus Logic

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WM8944B
Rev 4.3
113
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
011 = FVCO / 4
100 = FVCO / 5
101 = FVCO / 6
110 = FVCO / 7
111 = FVCO / 8
Recommended that this register is not changed from
default.
4:2
FLL_FRATIO
[2:0]
000
FVCO clock divider
000 = 1
001 = 2
010 = 4
011 = 8
1XX = 16
000 recommended for FREF > 1MHz
100 recommended for FREF < 16kHz
011 recommended for all other cases
1
FLL_FRAC
1
Fractional enable
0 = Integer Mode
1 = Fractional Mode
Integer mode offers reduced power consumption. Fractional
mode offers best FLL performance, provided also that N.K
is a non-integer value.
0
FLL_ENA
0
FLL Enable
0 = Disabled
1 = Enabled
Register 08h FLL Control 1
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R9 (09h) FLL
Control 2
15:0
FLL_K [15:0]
0011_0001
_0010_011
1
Fractional multiply for FREF
(MSB = 0.5)
Register 09h FLL Control 2
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R10 (0Ah)
FLL
Control 3
14:5
FLL_N [9:0]
00_0000_1
000
Integer multiply for FREF
(LSB = 1)
3:0
FLL_GAIN [3:0]
0000
Gain applied to error
0000 = x 1 (Recommended value)
0001 = x 2
0010 = x 4
0011 = x 8
0100 = x 16
0101 = x 32
0110 = x 64
0111 = x 128
1000 = x 256



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