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WM8944BECS/R 数据表(PDF) 110 Page - Cirrus Logic

部件名 WM8944BECS/R
功能描述  Mono Low-Power CODEC with Video Buffer
PDF  165 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

WM8944BECS/R 数据表(HTML) 110 Page - Cirrus Logic

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WM8944B
110
Rev 4.3
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
01 = Left Justified
10 = I2S format
11 = DSP/PCM mode
Register 04h Audio Interface
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R5 (05h)
Companding
control
15
ADC_DAC_
LOOPBACK
Digital Audio Interface Loopback Function
0 = No loopback
1 = Loopback enabled (ADC data is fed directly into DAC
data input).
5
LOOPBACK
0
Digital Loopback Function
0 = No loopback
1 = Loopback enabled (DACDAT input is fed through the
DSP Core to the ADCDAT output).
3
DAC_COMP
0
DAC Companding Enable
0 = Disabled
1 = Enabled
2
DAC_
COMPMODE
0
DAC Companding Mode
0 = µ-law
1 = A-law
1
ADC_COMP
0
ADC Companding Enable
0 = Disabled
1 = Enabled
0
ADC_
COMPMODE
0
ADC Companding Mode
0 = µ-law
1 = A-law
Register 05h Companding control
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R6 (06h)
Clock Gen
control
15
OSC_CLK_
ENA
0
Oscillator Enable
0 = Disabled
1 = Enabled
This needs to be set when a timeout clock is required for
GPIO input detection
14:13
MCLK_PULL
[1:0]
00
MCLK pull-up / pull-down Enable
00 = no pull-up or pull-down
01 = pull-down
10 = pull-up
11 = reserved
12
CLKOUT_SEL
0
CLKOUT Source Select
0 = SYSCLK
1 = FLL or MCLK (set by SYSCLK_SRC register)
11:10
CLKOUT_DIV
[1:0]
00
CLKOUT Clock divider
00 = divide by 1
01 = divide by 2
10 = divide by 4
11 = divide by 8



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