WM8944BECSSLASHR datasheet(112/165 Pages) CIRRUS

112 / 165 page

WM8944B

112

Rev 4.3

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

BIAS_ENA

0 = Disabled

1 = Enabled

BIAS_SRC

Bias Source select

0 = Master bias

1 = Start-Up bias

6:5

VMID_RAMP

[1:0]

VMID soft start enable / slew rate control

00 = Disabled

01 = Fast soft start

10 = Normal soft start

11 = Slow soft start

VMID_ENA

VMID Enable

0 = Disabled

1 = Enabled

3:0

SR [3:0]

1101

Audio Sample Rate select

0011 = 8kHz

0100 = 11.025kHz

0101 = 12kHz

0111 = 16kHz

1000 = 22.05kHz

1001 = 24kHz

1011 = 32kHz

1100 = 44.1kHz

1101 = 48kHz

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

R8 (08h) FLL

Control 1

12:11

FLL_CLK_REF_

DIV [1:0]

FLL Clock Reference Divider

00 = MCLK / 1

01 = MCLK / 2

10 = MCLK / 4

11 = MCLK / 8

MCLK (or other input reference) must be divided down to

<=13.5MHz.

For lower power operation, the reference clock can be

divided down further if desired.

10:8

FLL_OUTDIV

[2:0]

001

FOUT clock divider

000 = 2

001 = 4

010 = 8

011 = 16

100 = 32

101 = 64

110 = 6

111 = 12

(FOUT = FVCO / FLL_OUTDIV)

7:5

FLL_CTRL_

RATE [2:0]

000

Frequency of the FLL control block

000 = FVCO / 1 (Recommended value)

001 = FVCO / 2

010 = FVCO / 3

WM8944BECS/R 数据表(PDF) 112 Page - Cirrus Logic

WM8944BECS/R 数据表(HTML) 112 Page - Cirrus Logic

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