STR720 datasheet(216/401 Pages) STMICROELECTRONICS

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STR720 - CONTROLLER AREA NETWORK (CAN)

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Bit Timing Register (CAN_BTR)

Address Offset: 0Ch

Reset value: 2301h

Note

With a module clock APB_CLK of 8 MHz, the reset value of 0x2301 configures the

CAN Peripheral for a bit rate of 500 kBit/s. The registers are only writable if bits CCE

and Init in the CAN Control Register are set.

9876

res

TSeg2

TSeg1

SJW

BRP

Bit 15

Reserved

This is a reserved bit. This bit is always read as ‘0’ and must always be

written with ‘0’.

Bits 14:12

TSeg2: Time segment after sample point

0x0-0x7: Valid values for TSeg2 are [ 0 … 7 ]. The actual interpretation by

the hardware of this value is such that one more than the value

programmed here is used.

Bits 11:8

TSeg1: Time segment before the sample point minus Sync_Seg

0x01-0x0F: valid values for TSeg1 are [ 1 … 15 ]. The actual interpretation

by the hardware of this value is such that one more than the value

programmed is used.

Bits 7:6

SJW: (Re)Synchronization Jump Width

0x0-0x3: Valid programmed values are [ 0 … 3 ]. The actual interpretation

by the hardware of this value is such that one more than the value

programmed here is used.

Bits 5:0

BRP: Baud Rate Prescaler

0x01-0x3F: The value by which the oscillator frequency is divided for

generating the bit time quanta. The bit time is built up from a multiple of this

quanta. Valid values for the Baud Rate Prescaler are [ 0 … 63 ]. The actual

interpretation by the hardware of this value is such that one more than the

value programmed here is used.

STR720 数据表(PDF) 216 Page - STMicroelectronics

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