STR720 datasheet(232/401 Pages) STMICROELECTRONICS

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STR720 - CONTROLLER AREA NETWORK (CAN)

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18.5.4

Message Handler Registers

All Message Handler registers are read-only. Their contents, TxRqst, NewDat, IntPnd, and

MsgVal bits of each Message Object and the Interrupt Identifier is status information provided

by the Message Handler FSM.

Interrupt Identifier Register (CAN_IDR)

Address Offset: 10h

Reset value: 0000h

9876

5432

IntId[15:0]

Bits 15:0

IntId15:0 Interrupt Identifier (Table 52 indicates the source of the interrupt)

If several interrupts are pending, the CAN Interrupt Register will point to the

pending interrupt with the highest priority, disregarding their chronological

order. An interrupt remains pending until the application software has

cleared it. If IntId is different from 0x0000 and IE is set, the IRQ interrupt

signal to the EIC is active. The interrupt remains active until IntId is back to

value 0x0000 (the cause of the interrupt is reset) or until IE is reset.

The Status Interrupt has the highest priority. Among the message

interrupts, the Message Object’ s interrupt priority decreases with

increasing message number.

A message interrupt is cleared by clearing the Message Object’s IntPnd

bit. The Status Interrupt is cleared by reading the Status Register.

Table 52. Source of Interrupts

0x0000

No Interrupt is Pending

0x0001-0x0020

Number of Message Object which caused the interrupt.

0x0001-0x0020

Number of Message Object which caused the interrupt.

0x0021-0x7FFF

unused

0x8000

Status Interrupt

0x8001-0xFFFF

unused

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