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7.9.4.3 PLLs

Power is supplied to the Phase-Locked Loop circuitries (PLLs) by internal regulators that derive their power from

off-chip power sources.

There are total of three PLLs in the device in WKUP and MCU domains:

• MCU_PLL0 (MCU R5FSS PLL) with WKUP_PLLCTRL0

• MCU_PLL1 (MCU PERIPHERAL PLL)

• MCU_PLL2 (MCU CPSW PLL)

There are total of ten PLLs in MAIN domain:

• PLL0 (MAIN PLL) with PLLCTRL0

• PLL1 (PER0 PLL)

• PLL2 (PER1 PLL)

• PLL3 (CPSW5X PLL)

• PLL4 (AUDIO0 PLL)

• PLL7 (MSMC PLL)

• PLL8 (ARM0 PLL)

• PLL12 (DDR PLL)

• PLL13 (C66 PLL)

• PLL14 (R5FSS PLL)

Note

For more information, see:

• Device Configuration / Clocking / PLLs section in the device TRM.

• Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem - Gigabit

(PRU) section in the device TRM.

Note

The input reference clock (OSC1_XI/OSC1_XO) is specified and the lock time is ensured by the PLL

controller, as documented in the Device Configuration chapter in the device TRM.

7.9.4.4 Recommended Clock and Control Signal Transition Behavior

All clocks and strobe signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic

manner. Monotonic transitions are more easily ensured with faster switching signals. Slower input transitions are

more susceptible to glitches due to noise, and special care must be taken for slow input clocks.

7.9.4.5 Interface Clock Specifications

7.9.4.5.1 Interface Clock Terminology

The interface clock is used at the system level to sequence the data and to control transfers accordingly with the

interface protocol.

7.9.4.5.2 Interface Clock Frequency

The two interface clock characteristics are:

• The maximum clock frequency

• The maximum operating frequency

The interface clock frequency documented here is the maximum clock frequency, which corresponds to the

maximum frequency programmable on this output clock. This frequency defines the maximum limit supported by

the Device IC and does not take into account any system consideration (PCB, peripherals).

The system designer must take into account these system considerations and the Device IC timing

characteristics to properly define the maximum operating frequency that corresponds to the maximum frequency

supported to transfer the data on this interface.

DRA821U-Q1

SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022

www.ti.com

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