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DRA821U4...ALM 数据表(PDF) 146 Page - Texas Instruments |
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DRA821U4...ALM 数据表(HTML) 146 Page - Texas Instruments |
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146 / 252 page  NO. MODE MIN MAX UNIT D9 tw(bwsH) Pulse Duration, ATL_BWS[x] high(3) External reference clock 0.45 × B(2) + 2.5 ns (1) M = ATL_CLK[x] period (2) B = ATL_BWS[x] period (3) x = 0 to 3 7.9.5.1.4 ATCLK[x] Switching Characteristics NO. PARAMETER MODE MIN MAX UNIT D10 tc(atclk) Cycle time, ATCLK[x](3) Internal reference CLK 20 ns D11 tw(atclkL) Pulse Duration, ATCLK[x] low(3) Internal reference CLK 0.45 × P(2) - M(1) - 0.3 ns D12 tw(atclkH) Pulse Duration, ATCLK[x] high(3) Internal reference CLK 0.45 × P(2) - M(1) - 0.3 ns (1) M = ATL_CLK[x] period (2) P = ATCLK[x] period (3) x = 0 to 3 ATCLK[x] D12 D11 D10 atl_01 Figure 7-38. ATCLK[x] Timing 7.9.5.2 CPSW2G For more details about features and additional description information on the device Gigabit Ethernet MAC, see the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description. Table 7-26 represents CPSW2G timing conditions. Table 7-26. CPSW2G Timing Conditions PARAMETER DESCRIPTION MIN MAX UNIT INPUT CONDITIONS tR Input signal rise time 1 5 V/ns tF Input signal fall time 1 5 V/ns OUTPUT CONDITIONS CLOAD Output load capacitance 2 20 pF PCB CONNECTIVITY REQUIREMENTS td(Trace Mismatch Delay) Propagation delay mismatch across all traces RGMII[x]_RXC, RGMII[x]_RD[3:0], RGMII[x]_RX_CTL 50 ps RGMII[x]_TXC, RGMII[x]_TD[3:0], RGMII[x]_TX_CTL 50 ps 7.9.5.2.1 CPSW2G RMII Timings Section 7.9.5.2.1.1, Section 7.9.5.2.1.2, and Figure 7-39 present timing requirements for CPSW2G RMII receive. 7.9.5.2.1.1 Timing Requirements for RMII[x]_REFCLK – RMII Mode NO. PARAMETER DESCRIPTION MIN TYP MAX UNIT RMII1 tc(REF_CLK) Cycle time, REF_CLK 19.999 20.001 ns DRA821U-Q1 SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022 www.ti.com 146 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DRA821U-Q1 |
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