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DRA821U4...ALM 数据表(PDF) 142 Page - Texas Instruments |
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DRA821U4...ALM 数据表(HTML) 142 Page - Texas Instruments |
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142 / 252 page  VSS Device WKUP_LF_CLKIN J7VC_LF_OSC_INT_12 PCB Ground Figure 7-35. WKUP_LF_CLKIN Crystal Implementation Table 7-24 details the WKUP_LF_CLKIN input clock timing requirements.. Table 7-24. WKUP_LF_CLKIN Input Clock Timing Requirements (2) NAME DESCRIPTION MIN TYP MAX UNIT CK0 1 / tc(WKUP_LF_CLKIN ) Frequency, WKUP_LF_CLKIN 32768 Hz CK1 tw(WKUP_LF_CLKIN ) Pulse duration, WKUP_LF_CLKIN low or high 0.45*P(1) 0.55*P(1) ns (1) P is WKUP_LF_CLKIN cycle time in ns. (2) Refer to Section 7.6.7 LVCMOS Electrical Characteristics for voltage and slew rate information. WKUP_LF_CLKIN CK0 CK1 CK1 J7VC_WKUP_OSC_CLK_06 Figure 7-36. WKUP_LF_CLKIN Start-up Time 7.9.4.1.7 WKUP_LF_CLKIN Not Used Figure 7-37 shows the recommended oscillator connections when WKUP_LF_CLKIN is not used. WKUP_LF_CLKIN may be a no-connect while the oscillator remains disabled since the internal pull-down resistor is enabled by default. Device WKUP_LF_CLKIN J7VC_LF_OSC_NOT_USED_14 NC VSS PCB Ground Figure 7-37. WKUP_LF_CLKIN Not Used DRA821U-Q1 SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022 www.ti.com 142 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DRA821U-Q1 |
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