DRA821U4...ALM datasheet(150/252 Pages) TI

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7.9.5.2.2.4 Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL – RGMII Mode

NO.

PARAMETER

DESCRIPTION

MODE

MIN

TYP

MAX

UNIT

RGMII5 tosu(TD-TXC)

Output setup time, RGMII[x]_TD[3:0] valid to

RGMII[x]_TXC high/low

10Mbps

1.2

100Mbps

1.2

1000Mbps

1.05

tosu(TX_CTL-TXC)

Output setup time, RGMII[x]_TX_CTL valid to

RGMII[x]_TXC high/low

10Mbps

1.2

100Mbps

1.2

1000Mbps

1.05

RGMII6 toh(TD-TXC)

Output hold time, RGMII[x]_TD[3:0] valid after

RGMII[x]_TXC high/low

10Mbps

1.2

100Mbps

1.2

1000Mbps

1.0

toh(TX_CTL-TXC)

Output hold time, RGMII[x]_TX_CTL valid after

RGMII[x]_TXC high/low

10Mbps

1.2

100Mbps

1.2

1000Mbps

1.05

RGMII[x]_TXC

(A)

RGMII[x]_TD[3:0]

(B)

RGMII[x] TX_CTL

(B)

RGMII9

1st Half-byte

TXERR

TXEN

2nd Half-byte

RGMII7

RGMII8

RGMII6

RGMII10

TXC is delayed internally before being driven to the RGMII[x]_TXC pin. This internal delay is always enabled.

Data and control information is received using both edges of the clocks. RGMII_TD[3:0] carries data bits 3-0 on the rising edge of

RGMII_TXC and data bits 7-4 on the falling edge of RGMII_TXC. Similarly, RGMII_TX_CTL carries TXDV on rising edge of RGMII_TXC

and RTXERR on falling edge of RGMII_TXC.

Figure 7-43. CPSW2G Transmit Interface Timing RGMII Mode

For more information, see Gigabit Ethernet MAC (MCU_CPSW0) section in Peripherals chapter in the device

TRM.

7.9.5.3 CPSW5G

The Gigabit Ethernet MAC supports standards shown in Table 7-27.

Table 7-27. CPSW5G Supported Standards

INDUSTRIAL STANDARDS

BAUD(1)

LINK/ DATA RATE(1)

USXGMII/ XFI

5.15625 GBaud

10.3125 GBaud

5 Gbps

10 Gbps

QSGMII

5 GBaud

4x 1Gbps

XAUI (2.5G SGMII)

3.125 GBaud

2.5 Gbps

1G SGMII

1.25 GBaud

1 Gbps

(1)

Lower data rates are achieved through replication

For more details about features and additional description on the device Gigabit Ethernet MAC, see the

corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description.

Table 7-28 represents CPSW5G timing conditions.

DRA821U-Q1

SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022

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