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DRA821U4...ALM 数据表(PDF) 151 Page - Texas Instruments

部件名 DRA821U4...ALM
功能描述  DRA821 Jacinto™ Processors
PDF  252 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

DRA821U4...ALM 数据表(HTML) 151 Page - Texas Instruments

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Table 7-28. CPSW5G Timing Conditions
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
INPUT CONDITIONS
tR
Input signal rise time
1
5
V/ns
tF
Input signal fall time
1
5
V/ns
OUTPUT CONDITIONS
CLOAD
Output load capacitance
2
20
pF
PCB CONNECTIVITY REQUIREMENTS
td(Trace Mismatch Delay)
Propagation delay mismatch across
all traces
RGMII[x]_RXC,
RGMII[x]_RD[3:0],
RGMII[x]_RX_CTL
50
ps
RGMII[x]_TXC,
RGMII[x]_TD[3:0],
RGMII[x]_TX_CTL
50
ps
7.9.5.3.1 CPSW5G MDIO Interface Timings
Table 7-29, Table 7-30, Table 7-31, and Figure 7-44 present timing requirements for MDIO.
Table 7-29. CPSW5G MDIO Timing Conditions
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
INPUT CONDITIONS
SRI
Input signal slew rate
0.9
3.6
V/ns
OUTPUT CONDITIONS
CL
Output load capacitance
10
470
pF
Table 7-30. Timing Requirements for MDIO Input
NO.
PARAMETER
MIN
MAX
UNIT
MDIO1 tsu(MDIO_MDC)
Setup time, MDIO_DATA valid before MDIO_CLK high
90
ns
MDIO2 th(MDIO_MDC)
Hold time, MDIO_DATA valid after MDIO_CLK high
0
ns
Table 7-31. Switching Characteristics Over Recommended Operating Conditions for MDIO Output
NO.
PARAMETER
MIN
MAX
UNIT
MDIO3 tc(MDC)
Cycle time, MDIO_CLK
400
ns
MDIO4 tw(MDCH)
Pulse Duration, MDIO_CLK high
160
ns
MDIO5 tw(MDCL)
Pulse Duration, MDIO_CLK low
160
ns
MDIO6 tt(MDC)
Transition time, MDIO_CLK
5
ns
MDIO7 td(MDC_MDIO)
Delay time, MDIO_CLK High to MDIO_DATA valid
-150
150
ns
www.ti.com
DRA821U-Q1
SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022
Copyright © 2022 Texas Instruments Incorporated
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Product Folder Links: DRA821U-Q1



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