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DRA821U4...ALM 数据表(PDF) 152 Page - Texas Instruments |
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DRA821U4...ALM 数据表(HTML) 152 Page - Texas Instruments |
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152 / 252 page  MDIO3 MDIO1 MDIO2 MDIO7 MDIO4 MDIO5 MDIO[x]_MDC MDIO[x]_MDIO (input) MDIO[x]_MDIO (output) CPSW2G_MDIO_TIMING_01 Figure 7-44. CPSW5G MDIO Diagrams Receive and Transmit 7.9.5.3.2 CPSW5G RMII Timings Section 7.9.5.3.2.1, Section 7.9.5.3.2.2, and Figure 7-45 present timing requirements for CPSW5G RMII receive. 7.9.5.3.2.1 Timing Requirements for RMII[x]_REFCLK – RMII Mode NO. PARAMETER DESCRIPTION MIN TYP MAX UNIT RMII1 tc(REF_CLK) Cycle time, REF_CLK 19.999 20.001 ns RMII2 tw(REF_CLKH) Pulse Duration, REF_CLK High 7 13 ns RMII3 tw(REF_CLKL) Pulse Duration, REF_CLK Low 7 13 ns RMII[x]_REF_CLK RMII2 RMII3 RMII1 Figure 7-45. RMII[x]_REFCLK Timing – RMII Mode 7.9.5.3.2.2 Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER – RMII Mode NO. PARAMETER DESCRIPTION MIN TYP MAX UNIT RMII4 tsu(RXD-REF_CLK) Setup time, RXD[1:0] valid before REF_CLK 4 ns tsu(CRS_DV-REF_CLK) Setup time, CRS_DV valid before REF_CLK 4 ns tsu(RX_ER-REF_CLK) Setup time, RX_ER valid before REF_CLK 4 ns RMII5 th(REF_CLK-RXD) Hold time RXD[1:0] valid after REF_CLK 2 ns th(REF_CLK-CRS_DV) Hold time, CRS_DV valid after REF_CLK 2 ns th(REF_CLK-RX_ER) Hold time, RX_ER valid after REF_CLK 2 ns DRA821U-Q1 SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022 www.ti.com 152 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DRA821U-Q1 |
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