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DRA821U4...ALM 数据表(PDF) 155 Page - Texas Instruments |
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DRA821U4...ALM 数据表(HTML) 155 Page - Texas Instruments |
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155 / 252 page  7.9.5.3.3.4 Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL – RGMII Mode NO. PARAMETER DESCRIPTION MODE MIN TYP MAX UNIT RGMII5 tosu(TD-TXC) Output setup time, RGMII[x]_TD[3:0] valid to RGMII[x]_TXC high/low 10Mbps 1.2 ns 100Mbps 1.2 ns 1000Mbps 1.05 ns tosu(TX_CTL-TXC) Output setup time, RGMII[x]_TX_CTL valid to RGMII[x]_TXC high/low 10Mbps 1.2 ns 100Mbps 1.2 ns 1000Mbps 1.05 ns RGMII6 toh(TD-TXC) Output hold time, RGMII[x]_TD[3:0] valid after RGMII[x]_TXC high/low 10Mbps 1.2 ns 100Mbps 1.2 ns 1000Mbps 1.05 ns toh(TX_CTL-TXC) Output hold time, RGMII[x]_TX_CTL valid after RGMII[x]_TXC high/low 10Mbps 1.2 ns 100Mbps 1.2 ns 1000Mbps 1.05 ns RGMII[x]_TXC (A) RGMII[x]_TD[3:0] (B) RGMII[x] TX_CTL _ (B) RGMII9 1st Half-byte TXERR TXEN 2nd Half-byte RGMII7 RGMII8 RGMII6 RGMII10 A. TXC is delayed internally before being driven to the RGMII[x]_TXC pin. This internal delay is always enabled. B. Data and control information is received using both edges of the clocks. RGMII_TD[3:0] carries data bits 3-0 on the rising edge of RGMII_TXC and data bits 7-4 on the falling edge of RGMII_TXC. Similarly, RGMII_TX_CTL carries TXDV on rising edge of RGMII_TXC and RTXERR on falling edge of RGMII_TXC. Figure 7-48. CPSW5G Transmit Interface Timing RGMII Mode For more information, see Gigabit Ethernet Switch (CPSW0) section in Peripherals chapter in the device TRM. 7.9.5.4 DDRSS For more details about features and additional description information on the device LPDDR4 Memory Interfaces, see the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description. The device has dedicated interface to LPDDR4. It supports JEDEC JESD209-4B standard compliant LPDDR4 SDRAM devices with the following features: • 32-bit and 16-bit data path to external SDRAM memory • Memory device capacity: Up to 8GB address space available over two chip selects (4GB per rank) • No support for byte mode LPDDR4 memories, or memories with more than 17 row address bits Table 7-32 and Figure 7-49 present switching characteristics for DDRSS. Table 7-32. Switching Characteristics for DDRSS NO. PARAMETER DDR TYPE MIN MAX UNIT 1 tc(DDR_CKP/ DDR_CKN) Cycle time, DDR0_CKP and DDR0_CKN LPDDR4 0.625(1) 3.003 ns (1) Maximum DDR Frequency will be limited based on the specific memory type (vendor) used in a system and by PCB implementation.Maximum DDR Frequency will be limited based on the specific memory type (vendor) used in a system and by www.ti.com DRA821U-Q1 SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 155 Product Folder Links: DRA821U-Q1 |
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