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DRA821U4...ALM 数据表(PDF) 154 Page - Texas Instruments

部件名 DRA821U4...ALM
功能描述  DRA821 Jacinto™ Processors
PDF  252 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

DRA821U4...ALM 数据表(HTML) 154 Page - Texas Instruments

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NO.
PARAMETER
DESCRIPTION
MODE
MIN
TYP
MAX
UNIT
RGMII6 th(RXC-RD)
Hold time, RD[3:0] valid after RXC high/low
10Mbps
1
ns
100Mbps
1
ns
1000Mbps
1
ns
th(RXC-RX_CTL)
Hold time, RX_CTL valid after RXC high/low
10Mbps
1
ns
100Mbps
1
ns
1000Mbps
1
ns
RGMII7 tt(RD)
Transition time, RD
10Mbps
0.75
ns
100Mbps
0.75
ns
1000Mbps
0.75
ns
tt(RX_CTL)
Transition time, RX_CTL
10Mbps
0.75
ns
100Mbps
0.75
ns
1000Mbps
0.75
ns
RGMII[x] RD 3
_
[ :0]
(B)
RGMII[x] RX_CTL
_
(B)
RGMII[x] RXC
_
(A)
RGMII4
RXERR
RXDV
2nd Half-byte
1st Half-byte
RGMII2
RGMII3
RGMII1
RGMII5
A.
RGMII_RXC must be externally delayed relative to the data and control pins.
B.
Data and control information is received using both edges of the clocks. RGMII_RXD[3:0] carries data bits 3-0 on the rising edge of
RGMII_RXC and data bits 7-4 on the falling edge of RGMII_RXC. Similarly, RGMII_RXCTL carries RXDV on rising edge of RGMII_RXC
and RXERR on falling edge of RGMII_RXC.
Figure 7-47. CPSW5G Receive Interface Timing, RGMII Operation
Section 7.9.5.3.3.3, Section 7.9.5.3.3.4, and Figure 7-48 present switching characteristics for transmit - RGMII
for 10 Mbps, 100 Mbps, and 1000 Mbps.
7.9.5.3.3.3 Switching Characteristics for RGMII[x]_TCLK – RGMII Mode
NO.
PARAMETER
DESCRIPTION
MODE
MIN
TYP
MAX
UNIT
RGMII1 tc(TXC)
Cycle time, TXC
10Mbps
360
440
ns
100Mbps
36
44
ns
1000Mbps
7.2
8.8
ns
RGMII2 tw(TXCH)
Pulse duration, TXC high
10Mbps
160
240
ns
100Mbps
16
24
ns
1000Mbps
3.6
4.4
ns
RGMII3 tw(TXCL)
Pulse duration, TXC low
10Mbps
160
240
ns
100Mbps
16
24
ns
1000Mbps
3.6
4.4
ns
RGMII4 tt(TXC)
Transition time, TXC
10Mbps
0.75
ns
100Mbps
0.75
ns
1000Mbps
0.75
ns
DRA821U-Q1
SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022
www.ti.com
154
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Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: DRA821U-Q1



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