DRA821U4...ALM datasheet(163/252 Pages) TI

163 / 252 page

NO.

(2)

PARAMETER

DESCRIPTION

MODE(19)

MIN

MAX

MIN

MAX

UNIT

100 MHz

133 MHz

td(clkH-csnV)

Delay time, output clock GPMC_CLK

rising edge to output chip select

GPMC_CSn[i] transition(14)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1;

no extra_delay

-2.2+F

(6)

3.75+F

(6)

-2.2+F

(6)

3.75+F

(6)

td(clkH-CSn[i]V)

Delay time, output clock GPMC_CLK

rising edge to output chip select

GPMC_CSn[i] invalid(14)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1;

no extra_delay

-2.2+E

(5)

3.75+E

(5)

-2.2+E

(5)

3.75+E

(5)

td(aV-clk)

Delay time, output address

GPMC_A[27:1] valid to output clock

GPMC_CLK first edge

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2.3+B

(2)

4.5+B

(2)

-2.3+B

(2)

4.5+B

(2)

td(clkH-aIV)

Delay time, output clock GPMC_CLK

rising edge to output address

GPMC_A[27:1] invalid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2.3

4.5

-2.3

4.5

td(be[x]nV-clk)

Delay time, output lower byte

enable and command latch enable

GPMC_BE0n_CLE, output upper byte

enable GPMC_BE1n valid to output

clock GPMC_CLK first edge

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2.3+B

(2)

1.9+B

(2)

-2.3+B

(2)

1.9+B

(2)

td(clkH-be[x]nIV) Delay time, output clock GPMC_CLK

rising edge to output lower byte

enable and command latch enable

GPMC_BE0n_CLE, output upper byte

enable GPMC_BE1n invalid(11)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2.3+D

(4)

1.9+D

(4)

-2.3+D

(4)

1.9+D

(4)

td(clkL-be[x]nIV)

Delay time, GPMC_CLK falling edge

to GPMC_BE0n_CLE, GPMC_BE1n

invalid(12)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2.3+D

(4)

1.9+D

(4)

-2.3+D

(4)

1.9+D

(4)

td(clkL-be[x]nIV). Delay time, GPMC_CLK falling edge

to GPMC_BE0n_CLE, GPMC_BE1n

invalid(13)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2.3+D

(4)

1.9+D

(4)

-2.3+D

(4)

1.9+D

(4)

td(clkH-advn)

Delay time, output clock GPMC_CLK

rising edge to output address

valid and address latch enable

GPMC_ADVn_ALE transition

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1;

no extra_delay

-2.3+G

(7)

4.5+G

(7)

-2.3+G

(7)

4.5+G

(7)

td(clkH-advnIV)

Delay time, output clock GPMC_CLK

rising edge to output address

valid and address latch enable

GPMC_ADVn_ALE invalid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1;

no extra_delay

-2.3+D

(4)

4.5+D

(4)

-2.3+D

(4)

4.5+D

(4)

F10 td(clkH-oen)

Delay time, output clock GPMC_CLK

rising edge to output enable

GPMC_OEn_REn transition

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1;

no extra_delay

-2.3H(8)

3.5+H

(8)

-2.3H(8)

3.5+H

(8)

F11 td(clkH-oenIV)

Delay time, output clock GPMC_CLK

rising edge to output enable

GPMC_OEn_REn invalid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1;

no extra_delay

-2.3+E

(8)

3.5+E

(8)

-2.3+E

(8)

3.5+E

(8)

F14 td(clkH-wen)

Delay time, output clock GPMC_CLK

rising edge to output write enable

GPMC_WEn transition

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1;

no extra_delay

-2.3+I(9) 4.5+I(9)

-2.3+I

(9)

4.5+I(9)

F15 td(clkH-do)

Delay time, output clock GPMC_CLK

rising edge to output data

GPMC_AD[15:0] transition(11)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2.3+J

(10)

2.7+J

(10)

-2.3+J

(10)

2.7+J

(10)

F15 td(clkL-do)

Delay time, GPMC_CLK falling

edge to GPMC_AD[15:0] data bus

transition

(12)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2.3+J

(10)

2.7+J

(10)

-2.3+J

(10)

2.7+J

(10)

F15 td(clkL-do).

Delay time, GPMC_CLK falling

edge to GPMC_AD[15:0] data bus

transition(13)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2.3+J

(10)

2.7+J

(10)

-2.3+J

(10)

2.7+J

(10)

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DRA821U-Q1

SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022

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