DRA821U4...ALM datasheet(162/252 Pages) TI

162 / 252 page

7.9.5.9.1.1 GPMC and NOR Flash Timing Requirements — Synchronous Mode

NO.

PARAMETE

DESCRIPTION

MODE

(2)

MIN

MAX

MIN

MAX

UNIT

100 MHz

133 MHz

F12 tsu(dV-clkH)

Setup time, input data

GPMC_AD[15:0] valid before output

clock GPMC_CLK high

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

1.81

1.11

not_div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

1.06

F13 th(clkH-dV)

Hold time, input data GPMC_AD[15:0]

valid after output clock GPMC_CLK

high

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

1.78

2.28

not_div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

1.78

F21 tsu(waitV-clkH)

Setup time, input wait GPMC_WAIT[j]

valid before output clock GPMC_CLK

high

(1)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

1.81

1.11

not_div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

1.06

F22 th(clkH-waitV)

Hold time, input wait GPMC_WAIT[j]

valid after output clock GPMC_CLK

high

(1)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

1.78

2.28

not_div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

1.78

(1)

In GPMC_WAIT[j], j is equal to 0 or 1.

(2)

For div_by_1_mode:

•

GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:

–

GPMC_CLK frequency = GPMC_FCLK frequency

For not_div_by_1_mode:

•

GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 1h to 3h:

–

GPMC_CLK frequency = GPMC_FCLK frequency / (2 to 4)

For GPMC_FCLK_MUX:

•

CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = PER1_PLL_CLKOUT / 3 = 300 / 3 = 100MHz

For TIMEPARAGRANULARITY_X1:

•

GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/

WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,

OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,

WRDATAONADMUXBUS)

7.9.5.9.1.2 GPMC and NOR Flash Switching Characteristics – Synchronous Mode

NO.

(2)

PARAMETER

DESCRIPTION

MODE(19)

MIN

MAX

MIN

MAX

UNIT

100 MHz

133 MHz

1 / tc(clk)

Period, output clock GPMC_CLK(18)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

7.52

tw(clkH)

Typical pulse duration, output clock

GPMC_CLK high

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-0.3+

0.475*

P(15)

-0.3+

0.475*

P(15)

tw(clkL)

Typical pulse duration, output clock

GPMC_CLK low

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-0.3+

0.475*

P(15)

-0.3+

0.475*

P(15)

DRA821U-Q1

SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022

www.ti.com

162

Submit Document Feedback

Product Folder Links: DRA821U-Q1

DRA821U4...ALM 数据表(PDF) 162 Page - Texas Instruments

DRA821U4...ALM 数据表(HTML) 162 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

DRA821U4...ALM 数据表(PDF) 162 Page - Texas Instruments

DRA821U4...ALM 数据表(HTML) 162 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载