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DRA821U4...ALM 数据表(PDF) 161 Page - Texas Instruments |
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DRA821U4...ALM 数据表(HTML) 161 Page - Texas Instruments |
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161 / 252 page  Table 7-36. GPIO Timing Conditions (continued) PARAMETER BUFFER TYPE MIN MAX UNIT SRI Input slew rate LVCMOS 0.2 6.6 V/ns I2C OD FS 0.2 0.8 V/ns OUTPUT CONDITIONS CL Output load capacitance LVCMOS 3 10 pF I2C OD FS 3 100 pF Table 7-37. GPIO Timing Requirements NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT GPIO1 tw(GPIO_IN) Pulse width, GPIOn_x 1.8 V 2P + 2.6(1) ns 3.3 V 2P + 3.4(1) ns (1) P = functional clock period in ns. Table 7-38. GPIO Switching Characteristics NO. PARAMETER DESCRIPTION BUFFER TYPE MIN MAX UNIT GP3 tw(GPIO_OUT) Minimum Output Pulse Width LVCMOS -3.6 + 0.975P(1) ns GP4 tw(GPIO_OUT) Minimum Output Pulse Width Low I2C Open Drain 160 ns GP5 tw(GPIO_OUT) Minimum Output Pulse Width High I2C Open Drain 60 ns (1) P = functional clock period in ns. For more information, see General-Purpose Interface (GPIO) section in Peripherals chapter in the device TRM. 7.9.5.9 GPMC For more details about features and additional description information on the device General-Purpose Memory Controller, see the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description. Table 7-39. GPMC Timing Conditions PARAMETER DESCRIPTION MIN MAX UNIT Input Conditions SRI Input slew rate 1.65 4 V/ns Output Conditions CL Output load capacitance 5 20 pF PCB Connectivity Requirements td(Trace Delay) Propagation delay of each trace 133 MHz Synchronous Mode 140 360 ps All other modes 140 720 td(Trace Mismatch Delay) Propagation mismatch across all traces 200 ps 7.9.5.9.1 GPMC and NOR Flash — Synchronous Mode Section 7.9.5.9.1.1 and Section 7.9.5.9.1.2 assume testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 7-57 through Figure 7-61). www.ti.com DRA821U-Q1 SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 161 Product Folder Links: DRA821U-Q1 |
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