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ZUSBOPTSC01ZACG 数据表(PDF) 117 Page - Zilog, Inc. |
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ZUSBOPTSC01ZACG 数据表(HTML) 117 Page - Zilog, Inc. |
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117 / 282 page ![]() PS022827-1212 P R E L I M I N A R Y Operation Z8 Encore! XP® F082A Series Product Specification 100 Operation The UART always transmits and receives data in an 8-bit data format, least-significant bit first. An even or odd parity bit can be added to the data stream. Each character begins with an active Low start bit and ends with either 1 or 2 active High stop bits. Figures 11 and 12 display the asynchronous data format employed by the UART without parity and with par- ity, respectively. Figure 10. UART Block Diagram Receive Shifter Receive Data Transmit Data Transmit Shift TXD RXD System Bus Parity Checker Parity Generator Receiver Control Control Registers Transmitter Control CTS Status Register Register Register Register Baud Rate Generator DE with Address Compare |
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