ZUSBOPTSC01ZACG datasheet(114/282 Pages) ZILOG

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PS022827-1212

P R E L I M I N A R Y

Watchdog Timer Control Register

Z8 Encore! XP® F082A Series

Product Specification

Watchdog Timer Reload Upper, High and Low Byte Registers

The Watchdog Timer Reload Upper, High and Low Byte (WDTU, WDTH, WDTL) regis-

ters, shown in Tables 60 through 62, form the 24-bit reload value that is loaded into the

Watchdog Timer when a WDT instruction executes. The 24-bit reload value ranges across

bits [23:0] to encompass the three bytes {WDTU[7:0], WDTH[7:0], WDTL[7:0]}. Writ-

ing to these registers sets the appropriate reload value. Reading from these registers

returns the current Watchdog Timer count value.

The 24-bit WDT reload value must not be set to a value less than 000004H.

Table 60. Watchdog Timer Reload Upper Byte Register (WDTU)

Bit

Field

WDTU

RESET

00H

R/W

R/W*

Address

FF1H

Note: A read returns the current WDT count value; a write sets the appropriate reload value.

Bit

Description

[7:0]



WDTU

WDT Reload Upper Byte

Most-significant byte (MSB); bits[23:16] of the 24-bit WDT reload value.

Table 61. Watchdog Timer Reload High Byte Register (WDTH)

Bit

Field

WDTH

RESET

04H

R/W

R/W*

Address

FF2H

Note: A read returns the current WDT count value; a write sets the appropriate reload value.

Bit

Description

[7:0]



WDTH

WDT Reload High Byte

Middle byte; bits[15:8] of the 24-bit WDT reload value.

Caution:

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