ZUSBOPTSC01ZACG datasheet(112/282 Pages) ZILOG

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PS022827-1212

P R E L I M I N A R Y

Watchdog Timer Calibration

Z8 Encore! XP® F082A Series

Product Specification

WDT Reset in Normal Operation

If configured to generate a Reset when a time-out occurs, the Watchdog Timer forces the

device into the System Reset state. The WDT status bit in the Reset Status (RSTSTAT)

Recovery and Low Voltage Detection chapter on page 22.

WDT Reset in STOP Mode

If configured to generate a Reset when a time-out occurs and the device is in STOP Mode,

the Watchdog Timer initiates a Stop Mode Recovery. Both the WDT status bit and the

STOP

bit in the Reset Status (RSTSTAT) Register are set to 1 following WDT time-out in

STOP Mode.

Watchdog Timer Reload Unlock Sequence

Writing the unlock sequence to the Watchdog Timer (WDTCTL) Control Register address

unlocks the three Watchdog Timer Reload Byte registers (WDTU, WDTH and WDTL) to

allow changes to the time-out period. These write operations to the WDTCTL Register

address produce no effect on the bits in the WDTCTL Register. The locking mechanism

prevents spurious writes to the Reload registers. Observe the following steps to unlock the

Watchdog Timer Reload Byte registers (WDTU, WDTH and WDTL) for write access.

1. Write 55H to the Watchdog Timer Control Register (WDTCTL).

2. Write AAH to the Watchdog Timer Control Register (WDTCTL).

3. Write the Watchdog Timer Reload Upper Byte Register (WDTU) with the appropriate

time-out value.

4. Write the Watchdog Timer Reload High Byte Register (WDTH) with the appropriate

time-out value.

5. Write the Watchdog Timer Reload Low Byte Register (WDTL) with the appropriate

time-out value.



All three Watchdog Timer Reload registers must be written in the order just listed. There

must be no other register writes between each of these operations. If a register write

occurs, the lock state machine resets and no further writes can occur unless the sequence is

restarted. The value in the Watchdog Timer Reload registers is loaded into the counter

when the Watchdog Timer is first enabled and every time a WDT instruction is executed.

Watchdog Timer Calibration

Due to its extremely low operating current, the Watchdog Timer oscillator is somewhat

inaccurate. This variation can be corrected using the calibration data stored in the Flash

Information Page; see Tables 100 and 101 on page 173 for details. Loading these values

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