ZUSBOPTSC01ZACG datasheet(109/282 Pages) ZILOG

109 / 282 page

PS022827-1212

P R E L I M I N A R Y

Timer Control Register Definitions

Z8 Encore! XP® F082A Series

Product Specification

Timer 0–1 PWM High and Low Byte Registers

The Timer 0–1 PWM High and Low Byte (TxPWMH and TxPWML) registers, shown in

Tables 56 and 57, control Pulse-Width Modulator (PWM) operations. These registers also

store the Capture values for the CAPTURE and CAPTURE/COMPARE modes.

The TxPWMH and TxPWML registers also store the 16-bit captured timer value when

operating in CAPTURE or CAPTURE/COMPARE modes.

Table 56. Timer 0–1 PWM High Byte Register (TxPWMH)

Bit

Field

PWMH

RESET

00000000

R/W

R/WR/W

R/WR/WR/WR/WR/WR/W

Address

F04H, F0CH

Table 57. Timer 0–1 PWM Low Byte Register (TxPWML)

Bit

Field

PWML

RESET

00000000

R/W

R/WR/W

R/WR/WR/WR/WR/WR/W

Address

F05H, F0DH

Bit

Description

[7:0]



PWMH,

PWML

Pulse-Width Modulator High and Low Bytes

These two bytes, {PWMH[7:0], PWML[7:0]}, form a 16-bit value that is compared to the current

16-bit timer count. When a match occurs, the PWM output changes state. The PWM output

value is set by the TPOL bit in the Timer Control Register (TxCTL1) Register.

ZUSBOPTSC01ZACG 数据表(PDF) 109 Page - Zilog, Inc.

ZUSBOPTSC01ZACG 数据表(HTML) 109 Page - Zilog, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载