ZUSBOPTSC01ZACG datasheet(111/282 Pages) ZILOG

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PS022827-1212

P R E L I M I N A R Y

Operation

Z8 Encore! XP® F082A Series

Product Specification

Watchdog Timer Refresh

When first enabled, the Watchdog Timer is loaded with the value in the Watchdog Timer

Reload registers. The Watchdog Timer counts down to 000000H unless a WDT instruc-

tion is executed by the eZ8 CPU. Execution of the WDT instruction causes the downcoun-

ter to be reloaded with the WDT reload value stored in the Watchdog Timer Reload

registers. Counting resumes following the reload operation.

When the Z8 Encore! XP F082A Series devices are operating in DEBUG Mode (using the

on-chip debugger), the Watchdog Timer is continuously refreshed to prevent any Watch-

dog Timer time-outs.

Watchdog Timer Time-Out Response

The Watchdog Timer times out when the counter reaches 000000H. A time-out of the

Watchdog Timer generates either an interrupt or a system reset. The WDT_RES Flash

option bit determines the time-out response of the Watchdog Timer. For information about

programming the WDT_RES Flash option bit, see the Flash Option Bits chapter on

page 159.

WDT Interrupt in Normal Operation

If configured to generate an interrupt when a time-out occurs, the Watchdog Timer issues

an interrupt request to the interrupt controller and sets the WDT status bit in the Reset Sta-

tus (RSTSTAT) Register; see the Reset Status Register on page 29. If interrupts are

enabled, the eZ8 CPU responds to the interrupt request by fetching the Watchdog Timer

interrupt vector and executing code from the vector address. After time-out and interrupt

generation, the Watchdog Timer counter rolls over to its maximum value of FFFFFH and

continues counting. The Watchdog Timer counter is not automatically returned to its

reload value.

The Reset Status (RSTSTAT) Register must be read before clearing the WDT interrupt.

This read clears the WDT time-out Flag and prevents further WDT interrupts from imme-

diately occurring.

WDT Interrupt in STOP Mode

If configured to generate an interrupt when a time-out occurs and the Z8 Encore! XP

F082A Series devices are in STOP Mode, the Watchdog Timer automatically initiates a

Stop Mode Recovery and generates an interrupt request. Both the WDT status bit and the

STOP

bit in the Reset Status (RSTSTAT) Register are set to 1 following a WDT time-out

in STOP Mode. For more information about Stop Mode Recovery, see the Reset, Stop

Mode Recovery and Low Voltage Detection chapter on page 22.

If interrupts are enabled, following completion of the Stop Mode Recovery the eZ8 CPU

responds to the interrupt request by fetching the Watchdog Timer interrupt vector and exe-

cuting code from the vector address.

ZUSBOPTSC01ZACG 数据表(PDF) 111 Page - Zilog, Inc.

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