ZUSBOPTSC01ZACG datasheet(123/282 Pages) ZILOG

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PS022827-1212

P R E L I M I N A R Y

Operation

Z8 Encore! XP® F082A Series

Product Specification

106

In MULTIPROCESSOR (9-bit) Mode, the Parity (9th) bit location becomes the multipro-

cessor control bit. The UART Control 1 and Status 1 registers provide MULTIPROCES-

SOR (9-bit) Mode control and status information. If an automatic address matching

scheme is enabled, the UART Address Compare Register holds the network address of the

device.

MULTIPROCESSOR (9-bit) Mode Receive Interrupts

When MULTIPROCESSOR Mode is enabled, the UART only processes frames addressed

to it. The determination of whether a frame of data is addressed to the UART can be made

in hardware, software or some combination of the two, depending on the multiprocessor

configuration bits. In general, the address compare feature reduces the load on the CPU,

because it does not require access to the UART when it receives data directed to other

devices on the multi-node network. The following three MULTIPROCESSOR Modes are

available in hardware:

•

Interrupt on all address bytes

•

Interrupt on matched address bytes and correctly framed data bytes

•

Interrupt only on correctly framed data bytes



These modes are selected with MPMD[1:0] in the UART Control 1 Register. For all mul-

tiprocessor modes, bit MPEN of the UART Control 1 Register must be set to 1.

The first scheme is enabled by writing 01b to MPMD[1:0]. In this mode, all incoming

address bytes cause an interrupt, while data bytes never cause an interrupt. The interrupt

service routine must manually check the address byte that caused triggered the interrupt. If

it matches the UART address, the software clears MPMD[0]. Each new incoming byte

interrupts the CPU. The software is responsible for determining the end of the frame. It

checks for the end-of-frame by reading the MPRX bit of the UART Status 1 Register for

each incoming byte. If MPRX=1, a new frame has begun. If the address of this new frame

is different from the UART’s address, MPMD[0] must be set to 1 causing the UART inter-

rupts to go inactive until the next address byte. If the new frame’s address matches the

UART’s, the data in the new frame is processed as well.

The second scheme requires the following: set MPMD[1:0] to 10B and write the UART’s

address into the UART Address Compare Register. This mode introduces additional hard-

ware control, interrupting only on frames that match the UART’s address. When an

incoming address byte does not match the UART’s address, it is ignored. All successive

data bytes in this frame are also ignored. When a matching address byte occurs, an inter-

rupt is issued and further interrupts now occur on each successive data byte. When the first

data byte in the frame is read, the NEWFRM bit of the UART Status 1 Register is asserted.

All successive data bytes have NEWFRM=0. When the next address byte occurs, the hard-

ware compares it to the UART’s address. If there is a match, the interrupts continues and

the NEWFRM bit is set for the first byte of the new frame. If there is no match, the UART

ignores all incoming bytes until the next address match.

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