ZUSBOPTSC01ZACG datasheet(125/282 Pages) ZILOG

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PS022827-1212

P R E L I M I N A R Y

Operation

Z8 Encore! XP® F082A Series

Product Specification

108

UART Interrupts

The UART features separate interrupts for the transmitter and the receiver. In addition,

when the UART primary functionality is disabled, the Baud Rate Generator can also func-

tion as a basic timer with interrupt capability.

Transmitter Interrupts

The transmitter generates a single interrupt when the Transmit Data Register Empty bit

(TDRE) is set to 1. This indicates that the transmitter is ready to accept new data for trans-

mission. The TDRE interrupt occurs after the Transmit Shift Register has shifted the first

bit of data out. The Transmit Data Register can now be written with the next character to

send. This action provides 7 bit periods of latency to load the Transmit Data Register

before the Transmit Shift Register completes shifting the current character. Writing to the

UART Transmit Data Register clears the TDRE bit to 0.

Receiver Interrupts

The receiver generates an interrupt when any of the following actions occur:

•

A data byte is received and is available in the UART Receive Data Register. This inter-

rupt can be disabled independently of the other receiver interrupt sources. The received

data interrupt occurs after the receive character has been received and placed in the Re-

ceive Data Register. To avoid an overrun error, software must respond to this received

data available condition before the next character is completely received.

In MULTIPROCESSOR Mode (MPEN=1), the receive data interrupts are dependent on the

multiprocessor configuration and the most recent address byte.

•

A break is received.

•

An overrun is detected.

•

A data framing error is detected.

UART Overrun Errors

When an overrun error condition occurs the UART prevents overwriting of the valid data

currently in the Receive Data Register. The Break Detect and Overrun status bits are not

displayed until after the valid data has been read.

After the valid data has been read, the UART Status 0 Register is updated to indicate the

overrun condition (and Break Detect, if applicable). The RDA bit is set to 1 to indicate that

the Receive Data Register contains a data byte. However, because the overrun error

occurred, this byte may not contain valid data and must be ignored. The BRKD bit indi-

cates if the overrun was caused by a break condition on the line. After reading the status

Note:

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