ZUSBOPTSC01ZACG datasheet(127/282 Pages) ZILOG

127 / 282 page

PS022827-1212

P R E L I M I N A R Y

UART Control Register Definitions

Z8 Encore! XP® F082A Series

Product Specification

110

Rate Generator to function as an additional counter if the UART functionality is not

employed.

UART Baud Rate Generator

The UART Baud Rate Generator creates a lower frequency baud rate clock for data trans-

mission. The input to the Baud Rate Generator is the system clock. The UART Baud Rate

High and Low Byte registers combine to create a 16-bit baud rate divisor value

(BRG[15:0]) that sets the data transmission rate (baud rate) of the UART. The UART data

rate is calculated using the following equation:

When the UART is disabled, the Baud Rate Generator functions as a basic 16-bit timer

with an interrupt upon time-out. Observe the following steps to configure the Baud Rate

Generator as a timer with an interrupt upon time-out:

1. Disable the UART by clearing the REN and TEN bits in the UART Control 0 Register

to 0.

2. Load the acceptable 16-bit count value into the UART Baud Rate High and Low Byte

registers.

3. Enable the Baud Rate Generator timer function and associated interrupt by setting the

BRGCTL

bit in the UART Control 1 Register to 1.



When configured as a general purpose timer, the interrupt interval is calculated using the

following equation:

UART Control Register Definitions

The UART Control registers support the UART and the associated Infrared Encoder/

Decoders. For more information about infrared operation, see the Infrared Encoder/

Decoder chapter on page 120.

UART Control 0 and Control 1 Registers

The UART Control 0 (UxCTL0) and Control 1 (UxCTL1) registers, shown in Tables 63

and 64, configure the properties of the UART’s transmit and receive operations. The

UART Control registers must not be written while the UART is enabled.

UART Data Rate (bits/s)

System Clock Frequency (Hz)

UART Baud Rate Divisor Value



---------------------------------------------------------------------------------

Interrupt Interval s



System Clock Period (s)

BRG 15:0





ZUSBOPTSC01ZACG 数据表(PDF) 127 Page - Zilog, Inc.

ZUSBOPTSC01ZACG 数据表(HTML) 127 Page - Zilog, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载