ZUSBOPTSC01ZACG datasheet(130/282 Pages) ZILOG

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PS022827-1212

P R E L I M I N A R Y

UART Control Register Definitions

Z8 Encore! XP® F082A Series

Product Specification

113

[2]



BRGCTL

Baud Rate Control

This bit causes an alternate UART behavior depending on the value of the REN bit in the

UART Control 0 Register. When the UART receiver is not enabled (REN=0), this bit deter-

mines whether the Baud Rate Generator issues interrupts.

0 = Reads from the Baud Rate High and Low Byte registers return the BRG reload value.

1 = The Baud Rate Generator generates a receive interrupt when it counts down to 0.

Reads from the Baud Rate High and Low Byte registers return the current BRG count

value.

When the UART receiver is enabled (REN=1), this bit allows reads from the Baud Rate reg-

isters to return the BRG count value instead of the reload value.

0 = Reads from the Baud Rate High and Low Byte registers return the BRG reload value.

1 = Reads from the Baud Rate High and Low Byte registers return the current BRG count

value. Unlike the Timers, there is no mechanism to latch the Low Byte when the High

Byte is read.

[1]



RDAIRQ

Receive Data Interrupt Enable

0 = Received data and receiver errors generates an interrupt request to the Interrupt Con-

troller.

1 = Received data does not generate an interrupt request to the Interrupt Controller. Only

receiver errors generate an interrupt request.

[0]



IREN

Infrared Encoder/Decoder Enable

0 = Infrared Encoder/Decoder is disabled. UART operates normally.

1 = Infrared Encoder/Decoder is enabled. The UART transmits and receives data through

the Infrared Encoder/Decoder.

Bit

Description (Continued)

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