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ZUSBOPTSC01ZACG 数据表(PDF) 134 Page - Zilog, Inc. |
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ZUSBOPTSC01ZACG 数据表(HTML) 134 Page - Zilog, Inc. |
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134 / 282 page ![]() PS022827-1212 P R E L I M I N A R Y UART Control Register Definitions Z8 Encore! XP® F082A Series Product Specification 117 UART Baud Rate High and Low Byte Registers The UART Baud Rate High (UxBRH) and Low Byte (UxBRL) registers, shown in Tables 70 and 71, combine to create a 16-bit baud rate divisor value (BRG[15:0]) that sets the data transmission rate (baud rate) of the UART. Table 69. UART Address Compare Register (U0ADDR) Bit 7 6 5 4 3 2 1 0 Field COMP_ADDR RESET 00000000 R/W R/WR/W R/WR/WR/WR/WR/WR/W Address F45H Bit Description [7:0] COMP_ADDR Compare Address This 8-bit value is compared to incoming address bytes. Table 70. UART Baud Rate High Byte Register (U0BRH) Bit 7 6 5 4 3 2 1 0 Field BRH RESET 11111111 R/W R/WR/W R/WR/WR/WR/WR/WR/W Address F46H Bit Description [7:0] BRH UART Baud Rate High Byte Table 71. UART Baud Rate Low Byte Register (U0BRL) Bit 7 6 5 4 3 2 1 0 Field BRL RESET 11111111 R/W R/WR/W R/WR/WR/WR/WR/WR/W Address F47H Bit Description [7:0] BRL UART Baud Rate Low Byte |
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