ZUSBOPTSC01ZACG datasheet(132/282 Pages) ZILOG

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PS022827-1212

P R E L I M I N A R Y

UART Control Register Definitions

Z8 Encore! XP® F082A Series

Product Specification

115

UART Status 1 Register

This register contains multiprocessor control and status bits.

UART Transmit Data Register

Data bytes written to the UART Transmit Data (UxTXD) Register, shown in Table 67, are

shifted out on the TXDx pin. The Write-only UART Transmit Data Register shares a Reg-

ister File address with the read-only UART Receive Data Register.

[2]



TDRE

TDRE—Transmitter Data Register Empty

This bit indicates that the UART Transmit Data Register is empty and ready for additional data.

Writing to the UART Transmit Data Register resets this bit.

0 = Do not write to the UART Transmit Data Register.

1 = The UART Transmit Data Register is ready to receive an additional byte to be transmitted.

[1]



TXE

Transmitter Empty

This bit indicates that the Transmit Shift Register is empty and character transmission is finished.

0 = Data is currently transmitting.

1 = Transmission is complete.

[0]



CTS

CTS Signal

When this bit is read it returns the level of the CTS signal. This signal is active Low.

Table 66. UART Status 1 Register (U0STAT1)

Bit

Field

Reserved

NEWFRM

MPRX

RESET

00000000

R/W

RRRR

R/W

Address

F44H

Bit

Description

[7:2]

Reserved

These bits are reserved and must be programmed to 000000.

[1]



NEWFRM

New Frame

A status bit denoting the start of a new frame. Reading the UART Receive Data Register

resets this bit to 0.



0 = The current byte is not the first data byte of a new frame.



1 = The current byte is the first data byte of a new frame.

[0]



MPRX

Multiprocessor Receive

Returns the value of the most recent multiprocessor bit received. Reading from the UART

Receive Data Register resets this bit to 0.

Bit

Description (Continued)

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