ZUSBOPTSC01ZACG datasheet(129/282 Pages) ZILOG

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PS022827-1212

P R E L I M I N A R Y

UART Control Register Definitions

Z8 Encore! XP® F082A Series

Product Specification

112

Table 64. UART Control 1 Register (U0CTL1)

Bit

Field

MPMD[1]

MPEN

MPMD[0]

MPBT

DEPOL

BRGCTL

RDAIRQ

IREN

RESET

00000000

R/W

R/WR/W

R/WR/WR/WR/WR/WR/W

Address

F43H

Bit

Description

[7,5]



MPMD[1,0]

MULTIPROCESSOR Mode

If MULTIPROCESSOR (9-bit) Mode is enabled:

00 = The UART generates an interrupt request on all received bytes (data and address).

01 = The UART generates an interrupt request only on received address bytes.

10 = The UART generates an interrupt request when a received address byte matches the

value stored in the Address Compare Register and on all successive data bytes until

an address mismatch occurs.

11 = The UART generates an interrupt request on all received data bytes for which the most

recent address byte matched the value in the Address Compare Register.

[6]



MPEN

MULTIPROCESSOR (9-bit) Enable

This bit is used to enable MULTIPROCESSOR (9-bit) Mode.



0 = Disable MULTIPROCESSOR (9-bit) Mode.



1 = Enable MULTIPROCESSOR (9-bit) Mode.

[4]



MPBT

Multiprocessor Bit Transmit

This bit is applicable only when MULTIPROCESSOR (9-bit) Mode is enabled. The 9th bit is

used by the receiving device to determine if the data byte contains address or data informa-

tion.



0 = Send a 0 in the multiprocessor bit location of the data stream (data byte).



1 = Send a 1 in the multiprocessor bit location of the data stream (address byte).

[3]



DEPOL

Driver Enable Polarity

0 = DE signal is Active High.



1 = DE signal is Active Low.

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