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ZUSBOPTSC01ZACG 数据表(PDF) 135 Page - Zilog, Inc.

部件名 ZUSBOPTSC01ZACG
功能描述  High-Performance 8-Bit Microcontrollers
PDF  282 Pages
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制造商  ZILOG [Zilog, Inc.]
网页  http://www.zilog.com
标志 ZILOG - Zilog, Inc.

ZUSBOPTSC01ZACG 数据表(HTML) 135 Page - Zilog, Inc.

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PS022827-1212
P R E L I M I N A R Y
UART Control Register Definitions
Z8 Encore! XP® F082A Series
Product Specification
118
The UART data rate is calculated using the following equation:
For a given UART data rate, calculate the integer baud rate divisor value using the follow-
ing equation:
The baud rate error relative to the acceptable baud rate is calculated using the following
equation:
For reliable communication, the UART baud rate error must never exceed 5 percent.
Table 72 provides information about the data rate errors for popular baud rates and com-
monly used crystal oscillator frequencies.
Table 72. UART Baud Rates
10.0MHz System Clock
5.5296MHz System Clock
Acceptable
Rate (kHz)
BRG Divisor
(Decimal)
Actual Rate
(kHz)
Error
(%)
Acceptable
Rate (kHz)
BRG Divisor
(Decimal)
Actual Rate
(kHz)
Error
(%)
1250.0
N/A
N/A
N/A
1250.0
N/A
N/A
N/A
625.0
1
625.0
0.00
625.0
N/A
N/A
N/A
250.0
3
208.33
–16.67
250.0
1
345.6
38.24
115.2
5
125.0
8.51
115.2
3
115.2
0.00
57.6
11
56.8
–1.36
57.6
6
57.6
0.00
38.4
16
39.1
1.73
38.4
9
38.4
0.00
19.2
33
18.9
0.16
19.2
18
19.2
0.00
9.60
65
9.62
0.16
9.60
36
9.60
0.00
4.80
130
4.81
0.16
4.80
72
4.80
0.00
2.40
260
2.40
–0.03
2.40
144
2.40
0.00
1.20
521
1.20
–0.03
1.20
288
1.20
0.00
0.60
1042
0.60
–0.03
0.60
576
0.60
0.00
0.30
2083
0.30
0.2
0.30
1152
0.30
0.00
3.579545MHz System Clock
1.8432MHz System Clock
UART Baud Rate (bits/s)
System Clock Frequency (Hz)
16
UART Baud Rate Divisor Value
------------------------------------------------------------------------------------------------
=
UART Baud Rate Divisor Value (BRG)
Round
System Clock Frequency (Hz)
16
UART Data Rate (bits/s)
-------------------------------------------------------------------------------


=
UART Baud Rate Error (%)
100
Actual Data Rate
Desired Data Rate
–
Desired Data Rate
----------------------------------------------------------------------------------------------------


=



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