ZUSBOPTSC01ZACG datasheet(124/282 Pages) ZILOG

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PS022827-1212

P R E L I M I N A R Y

Operation

Z8 Encore! XP® F082A Series

Product Specification

107

The third scheme is enabled by setting MPMD[1:0] to 11b and by writing the UART’s

address into the UART Address Compare Register. This mode is identical to the second

scheme, except that there are no interrupts on address bytes. The first data byte of each

frame remains accompanied by a NEWFRM assertion.

External Driver Enable

The UART provides a Driver Enable (DE) signal for off-chip bus transceivers. This fea-

ture reduces the software overhead associated with using a GPIO pin to control the trans-

ceiver when communicating on a multi-transceiver bus, such as RS-485.

Driver Enable is an active High signal that envelopes the entire transmitted data frame

including parity and Stop bits as displayed in Figure 14. The Driver Enable signal asserts

when a byte is written to the UART Transmit Data Register. The Driver Enable signal

asserts at least one UART bit period and no greater than two UART bit periods before the

Start bit is transmitted. This allows a setup time to enable the transceiver. The Driver

Enable signal deasserts one system clock period after the final Stop bit is transmitted. This

one system clock delay allows both time for data to clear the transceiver before disabling

it, plus the ability to determine if another character follows the current character. In the

event of back to back characters (new data must be written to the Transmit Data Register

before the previous character is completely transmitted) the DE signal is not deasserted

between characters. The DEPOL bit in the UART Control Register 1 sets the polarity of

the Driver Enable signal.

The Driver Enable-to-Start bit setup time is calculated as follows:

Figure 14. UART Driver Enable Signal Timing (shown with 1 Stop Bit and Parity)

Start

Bit0

Bit1

Bit2

Bit3

Bit4

Bit5

Bit6

Bit7

Parity

Data Field

lsb

msb

Idle State

of Line

Stop Bit

Baud Rate (Hz)

-----------------------------------------





DE to Start Bit Setup Time (s)

Baud Rate (Hz)

-----------------------------------------







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