ZUSBOPTSC01ZACG datasheet(153/282 Pages) ZILOG

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PS022827-1212

P R E L I M I N A R Y

ADC Control Register Definitions

Z8 Encore! XP® F082A Series

Product Specification

136

ADC Data High Byte Register

The ADC Data High Byte (ADCD_H) Register contains the upper eight bits of the ADC

output. The output is an 13-bit two’s complement value. During a single-shot conversion,

this value is invalid. Access to the ADC Data High Byte Register is read-only. Reading the

ADC Data High Byte Register latches data in the ADC Low Bits Register.

Table 74. ADC Control/Status Register 1 (ADCCTL1)

Bit

Field

REFSELH

Reserved

BUFMODE[2:0]

RESET

10000000

R/W

R/WR/W

R/WR/WR/WR/WR/WR/W

Address

F71H

Bit

Description

[7]



REFSELH

Voltage Reference Level Select High Bit

In conjunction with the Low bit (REFSELL) in ADC Control Register 0, this determines

the level of the internal voltage reference; the following details the effects of {REFSELH,

REFSELL}; this reference is independent of the Comparator reference.

00= Internal Reference Disabled, reference comes from external pin.



01= Internal Reference set to 1.0V.



10= Internal Reference set to 2.0V (default).



11= Reserved.

[6:3]

Reserved

These bits are reserved and must be programmed to 0000.

[2:0]



BUFMODE[2:0]

Input Buffer Mode Select

000 = Single-ended, unbuffered input.



001 = Single-ended, buffered input with unity gain.



010 = Reserved.



011 = Reserved.



100 = Differential, unbuffered input.



101 = Differential, buffered input with unity gain.



110 = Reserved.



111 = Reserved.

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