STR720 datasheet(116/401 Pages) STMICROELECTRONICS

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STR720 - EXTERNAL MEMORY INTERFACE (EMI)

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11.3 Functional Description

The External Memory Interface is a configurable peripheral aimed to ease the connection of

external memory components. EMI memory map is detailed in Table 31. Each memory

address region (Bank), with the exception of Bank 0, has a configurable base address (with a

granularity of 2k in the 8M total address space) and a configurable size. For bank 1 base

address is selected via a dedicated 16-bit register (BBASE1) that defines the upper 16 bits of

the range over which the relevant chip select will be active.

For bank 1 the user has the freedom of independently choosing bank start address and bank

size. Since the physical address going to the external memory (EAdd[22:1]) is simply obtained

by dropping bits from 31 to 23 of the AHB address, it may happen that the lowest address of

the bank does not map to the lowest address of the external memory. This does not mean that

the one-to-one correspondence between an address and a physical location in the memory is

lost: it means only that lowest address of the bank (as defined by bbase) will map somewhere

in the middle of the memory and that, after reaching the top of the physical memory, the

address will wrap around to zero.

In the special case in which the bank start address is programmed to be a multiple of the bank

length, the usual result of having the lowest address of the bank mapped to the lowest

address of the external memory is obtained. Therefore, to get this usual mapping, a 64 kbyte

memory should be only mapped at 64k boundaries, a 128 kbyte memory should be only

mapped at 128k boundaries and so on. It is up to the user the consistent programming of the

“base” and “length” registers.

11.3.1

EMI Programmable Timings

Each memory bank of the EMI can have a programmable number of wait states (up to 7)

added to any read or write cycle: this is accomplished via the C_LENGTH bitfield of the

BCONx register (x=0,..,1).

This C_SETUP programing will translate in different cycle lengths, depending on the Read or

Write type of operation and depending on the bank on which the operation is performed.

For write cycles which translate in a single external bus operation (e.g. a 16-bit write), the total

length (measured in EMI internal clock units) that a single access will require (equal to the

length over which the Chip Select will be active) will depend on the memory bank the cycle is

executed on. It can be calculated through the formula:

Setup Write Enable Time

Hold

CS Length (Write, Bank 0/1) = 0

+ (C_LENGTH+1)

+ 1

Table 31. EMI Address Map

Bank Start Address

Description

Size

Bus Width

0b_0

Bank 0 (CS0)

64k - 8M

0b_BBASE1[11:0] | 000_0000_0000

Bank 1 (CS1)

64k - 8M

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