STR720 datasheet(119/401 Pages) STMICROELECTRONICS

119 / 401 page

STR720 - EXTERNAL MEMORY INTERFACE (EMI)

119/401

internally in the EMI block (In this case - “DAAD” - i.e 16 LSBs of EDATA) so that the correct

data (i.e “6FF6DAAD”) is output on the AHB Data Bus (“HRDATA”).

For the 1st read operation, EAdd[1] is assigned “0”, for the second this is changed in “1”.

Since C_LENGTH = 1, total length of access is 6 AHB_CLK cycles, first word is sampled

3 AHB_CLK cycles after chip select activation and second word is sample 2 AHB_CLK cycles

after valid address (see formulas in Section 11.3.1:

EMI Programmable Timings on

page 116). In this example the minimum time for a read cycle is 2 AHB_CLK cycles.

Note

It must be noted that when a 32-bit access cycle is requested, Ecsxn line remains

active low across the two 16-bit cycles automatically generated by EMI where only bit

0 of Eadd bus changes. As a consequence EMI should be used in this configuration

only with external memory devices that do not latch the address bus on the Ecsxn

falling edge, but instead change their output bus data directly following the address

bus change while Ecsxn is kept low. This capability is often referred to as “Array data

reading” in memory device datasheets.

Figure 12. 32-bit Read cycle on 16-bit memory bus

AHB_CLK

C_Length[2:0]

Ecs0n

Ewr0n

Ewr1n

Eadd[21:1]

Edata[15:0]

Erdn

(Input)

AHB address[22:2]

0x0

DAADH

Total Access Length (1 Wait States,)

6FF6H

0x0

0x1

Eadd[0]

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