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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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STR720 数据表(PDF) 121 Page - STMicroelectronics |
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STR720 数据表(HTML) 121 Page - STMicroelectronics |
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121 / 401 page  STR720 - EXTERNAL MEMORY INTERFACE (EMI) 121/401 Bit 5 BE: Bank 0 Enable. BE bit enables Bank 0 of memory. = 1. Bank enabled. = 0. Bank disabled. Bit 4:2 C_LENGTH[2:0]: Cycle Length. The C_LENGTH field selects the number of wait states that will be inserted in any read/write cycle performed in memory Bank 0. The total CS length of any read or write cycle will be equal to C_LENGTH+2 periods of the EMI internal clock. = 0x0. 0 wait states. = 0x1. 1 wait state. = 0x2. 2 wait states. = 0x3. 3 wait states. .... = 0x7. 7 wait states. Bit 1 Reserved. This bit must be always written to ‘0’. Bit 0 Reserved. This bit must be always written to ‘1’. Note When asynchronous ready operation is configured (EREN = 1 and ISYN0 = 0) the number of wait states configured in C_LENGTH field must be greater than 4. 1 |
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