STR720 datasheet(125/401 Pages) STMICROELECTRONICS

125 / 401 page

STR720 - EXTERNAL MEMORY INTERFACE (EMI)

125/401

11.5 Programming considerations

EMI programming and usage is accomplished via the configuration, status and data registers

described in previous paragraphs.

At reset time all the EMI registers will be reset to 0x0001 or 0x0000 with the exception of the

Bank 0 Configuration Register (BCON0) which, out of reset, will be in the following condition:

■

BCON0[15:8]: Bank Length (B_LENGTH0) = 0x7F (8M bytes).

■

BCON0[7]: External Ready Enable (EREN) = 0. External Ready not used.

■

BCON0[6]: Internal Synchronization (ISYN0) = 0. No internal synchronization of Eready.

■

BCON0[5]: Bank Enable (BE) = 1. Bank 0 is enabled.

■

BCON[4:2]: Cycle Length (C_LENGTH) = 0x7. Maximum number of wait states (7).

A special care must be taken on bit 0 of each BCONx register, which must be always written

at ‘1’ to assure a correct functionality of the EMI cell. This is true also for the reserved

locations at the offset 08h and 0Ch respectively.

The EREN (External Ready Enable) bit in BBCON registers should be set only if the device

connected externally does have an access time that is variable. If set, ONLY at the end of the

programmed number of wait states, the status of the Eready signal will be checked: if it is low

a further wait state will be inserted and the process will continue until Eready is sampled high.

If EREN is cleared, the status of Eready will be ignored an the read/write cycles will always be

completed in the programmed number of wait states.

Since the usage of Eready implies the sampling of an external signal, the user has two

options, selected by the status of the ISYN bit. If ISYN=0, this provides the fastest bus cycle

but requires that setup and hold times are met with respect to internal peripheral clock. If

ISYN=1, Eready is internally synchronized by additional logic, but this will cause additional

wait states determined by the internal synchronization process. When ISYN is 0, Eready is not

internally resampled so to be sure that it is correctly detected by EMI logic, the number of

configured wait states cannot be lower than 4.

The start address and extension of both address regions can be configured via configuration

registers. However is up to the user to program them consistently, avoiding overlapping in

areas where more than one chip select could be active. A simple mechanism is anyway

implemented to avoid possible damages to the external components deriving from this

(unwanted) condition: a priority does exist such that no more than one chip select can be

active at any time. The priority scheme is as follows:

■

CS0 (Highest Priority)

■

CS1 (Lowest Priority)

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