STR720 datasheet(127/401 Pages) STMICROELECTRONICS

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STR720 - ATAPI-IDE INTERFACE

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12.3 Functional Description

The ATAPI-IDE interface allows the application to communicate with an external ATAPI-IDE

device via PBI. The 82371-type IDE is connected to the AHB bus as a slave. Operation of the

interface is independent of the AHB_CLK:PBI ratio, typical ratios will be 2:1 or 3:1.

Figure 13. ATAPI-IDE Interface overview Block Diagram

AHB Wait states are inserted until the ATAPI-IDE interface has responded to the transaction.

The number of wait states will vary depending on the clock ratio and on the stage of the PBI

cycle in which the AHB transaction is initiated. Typical values will be 3 or 4 wait states for a

ratio of 2:1, and 5 or 6 wait states for a divide ratio of 3:1.

The above assumes that the PBI does not insert any wait states. For each cycle the PBI

de-asserts the RDY signal, the AHB will have additional wait states equivalent to the divide

ratio inserted. i.e. 2 for 2:1, 3 for 3:1 etc.

IDD[0:15]

IDA[0:2]

IDiorn

IDiown

ICs0n

ICs1n

IOrdy

ATAPI IDE

DEVICE

IRQ15 to EIC

82371 ATAPI IDE

Irq

IDE

CONFIGURATION

IDE COMMAND

ATAPICLK

(FROM RCCU)

PBI CLK

Clock Gating Bit

Peripheral Under Reset Bit

(A3BRG_PUR0 register)

(A3BRG_PCG0 register)

STR720

STR720 数据表(PDF) 127 Page - STMicroelectronics

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