STR720 datasheet(128/401 Pages) STMICROELECTRONICS

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STR720 - ATAPI-IDE INTERFACE

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12.4 Programming Considerations

This section gives a brief overview of the interaction between the ATAPI-IDE controller and the

STR720.

12.4.1

Initialization

Due to the fact that this ATAPI-IDE interface is synchronously reset, all its output signals will

remain undefined until a valid clock signal is supplied, regardless of the state of its reset input.

As a consequence, when initializing the system to use the ATAPI-IDE interface, the following

procedure should be followed:

1. Remove IDE specific reset (controlled by the A3BRG_PUR0 register).

2. Enable AHB clock to the ATAPI IDE Interface (using the A3BRG_PCG0 register).

3. Enable IDE related interrupt, if required (IRQ 15). Refer to the Enhanced Interrupt Con-

troller Chapter).

4. Configure the I/O Port Registers

5. Configure Port 7 for IDE via the P7AS bit in the Miscellanea Global configuration Register

6. Set up IDE controller by programming its configuration registers located from offset 100h

to 144h. Refer to Section 12.5.2.1 .

12.4.2

Basic Read Transfer

1. When a read access to the external IDE device is required, the related IDE Command

registers should be programmed accordingly, for example by writing the physical address

of the device location to be accessed (sector, cylinder, head) and starting the IDE device

seek operation.

2. The IDE device flags any relevant event on its side by a rising edge on the interrupt line

(P7.45 pin). This will generate an IRQ15 interrupt request to the core if the corresponding

interrupt mask bit is enabled. Refer to the EIC register description.

3. In the interrupt service routine the application checks the IDE Status Register to deter-

mine which event triggered the interrupt request.

4. If the access to the requested location IDE reported as successful, the data can be

fetched through the IDE data register.

If DMA is used, the application then requests the DMA controller to perform a “mem-

ory-to-memory” transfer from the IDE data register (offset 010h) to the buffer in system

memory where data is to be stored.

5. The end of transfer will be flagged by the DMA interrupt, notifying that the programmed

number of words has been stored in the memory buffer.

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