STR720 datasheet(129/401 Pages) STMICROELECTRONICS

129 / 401 page

STR720 - ATAPI-IDE INTERFACE

129/401

12.5 Register map

The register map is split into two sections. One for IDE Command registers and the other for

IDE Configuration registers. Bit 8 of the location address is used to decode which bank of

registers is being accessed, as it is indicated by the address offset reported in the following

tables. All addresses specified for the two register blocks are expressed as offsets with

respect to the ATAPI-IDE register base address located at 0xC000_0000.

12.5.1.1 IDE Command Register Access

Although the IDE Command registers are mapped on byte locations in the STR720 memory map they do

not behave in the same way as other memory locations. Accessing a register causes the IDE interface to

fetch the selected register from the external IDE device.

The IDE Command registers are accessed individually. This means that it is not possible to access more

than one register with a single instruction, even using a 16 or 32- bit instruction.

A word access to Cylinder low, will not access Cylinder high etc.

The IDE data register is different from the other registers in the command register block. Although the data

access results in two 16-bit accesses to the IDE device to complete the word on the AHB bus. A half word

access results in one access to the device returning 16 bits of Data.

12.5.1

IDE Command Block Register Set

Addr.

Offset

5432

000h-

00fh

Reserved

Primary IDE Port Command/Data

010h

Data

DATA (rw)

011h Error/Features

ERROR (r) / FEATURES (w)

012h

Sector Count

SECTOR COUNT (rw)

013h Sector Number

SECTOR NUMBER LBA [7:0] (rw)

014h

Cylinder Low

CYLINDER LOW LBA [15:8] (rw)

015h Cylinder High

CYLINDER HIGH LBA [23:16] (rw)

016h

Device Head

DEVICE / HEAD LBA [27:24] (rw)

017h

Status/

Command

STATUS (r) / COMMAND (w)

018h

025h

Reserved

Primary IDE Port Control/Status

026h

Alternate Sta-

tus/

Device Control

ALTERNATE STATUS (r) / DEVICE CONTROL (w)

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