STR720 datasheet(132/401 Pages) STMICROELECTRONICS

部件名	STR720

功能描述	ARM720T 16/32-BIT MCU WITH 16K RAM, USB, CAN, 3 TIMERS, ADC, 6 COMMUNICATIONS INTERFACES

PDF	401 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

标志

132 / 401 page

STR720 - ATAPI-IDE INTERFACE

132/401

Status (XSTS)

Address Offset: 106h

Reset value:

Bits 8:0 = Reserved. Must be kept at reset value.

Bits 10:9 = DEVTS: Devsel Timing Status.

01 indicates medium speed timing.

Bit 11 = STAS: Signaled Target Abort Status.

Set when the ATAPI-IDE interface signals a transaction abort (ABORT signal)

Bit 12 = RTA: Receive Target Abort.

Set when the ATAPI-IDE interface receives a target abort (MTABORT signal).

Bit 13 = MTAS: Master Abort Status.

Set when the ATAPI-IDE interface generates a master abort.

Bits 15:14 = Reserved. Must be kept at reset value.

Note

Bits 13, 12 and 11 are Read and Clear (rc). The bit may be read, the read having no

effect on the register value. Writing “0” to the bit has no effect; writing “1” will clear the

bit.

Revision ID (REVID)

Address Offset: 108h

Reset value: 01h

Bits 7:0 = Revision Identification Number

6543210

Reserved

MAS

RTA

STAS

Devsel Timing

Status

Reserved

-rc

Revision Identification Number

STR720 数据表(PDF) 132 Page - STMicroelectronics