STR720 datasheet(134/401 Pages) STMICROELECTRONICS

134 / 401 page

STR720 - ATAPI-IDE INTERFACE

134/401

Primary IDE Timing (PIDETIM)

Address Offset: 140h

Reset value: 00h

Bit 0 = FTB0: Drive 0 Fast Timing Bank Select.

0: Use 16-bit compatible timings to the Data Port for Drive 0

1: Use timing for Drive 0 defined by bit 3 (TIM0)

Bit 1 =RDY0EN: Drive 0 IOrdy Sampling Enable

0: Disable IOrdy Sampling for Drive 0

1: Enable IOrdy Sampling for Drive 0

Bit 2 = PP0EN: Drive 0 Prefetch and Posting Enable

0: Disable Prefetch and Posting for Drive 0

1: Enable Prefetch and Posting for Drive 0

Bit 3 = TIM0: Drive 0 Timing Select

0: PIO transfers use fast timing for Drive 0

1: PIO transfers use Mode 0 compatible timing for Drive 0

Bit 4 = FTB1: Drive 1 Fast Timing Bank Select.

0: Use 16-bit compatible timings to the Data Port for Drive 1

1: Use timing for Drive 1 defined by bit 7 (TIM1)

Bit 5 = RDY1EN: Drive 1 IOrdy Sampling Enable

0: Disable IOrdy Sampling for Drive 1

1: Enable IOrdy Sampling for Drive 1

Bit 6 = PP1EN: Drive 1 Prefetch and Posting Enable

0: Disable Prefetch and Posting for Drive 1

1: Enable Prefetch and Posting for Drive 1

Bit 7 = TIM1: Drive 1 Timing Select

0: PIO transfers use fast timing for Drive 1

1: PIO transfers use Mode 0 compatible timing for Drive 1

Bits 9:8 = RCTP: Recovery Time.

Defines the minimum number of clock periods inactive between successive cycles: 00=4,

01=3,10=2, 11=1

Bits 11:10 = Reserved. Must be kept at reset value.

DCDEN STEN

ISPP

Reserved

RCTP

TIM1

PP1EN RDY1EN

FTB1

TIM0

PP0EN RDY0EN

FTB0

rwrw

rwrwrw

STR720 数据表(PDF) 134 Page - STMicroelectronics

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