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STR720 数据表(PDF) 130 Page - STMicroelectronics

部件名 STR720
功能描述  ARM720T 16/32-BIT MCU WITH 16K RAM, USB, CAN, 3 TIMERS, ADC, 6 COMMUNICATIONS INTERFACES
PDF  401 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STR720 数据表(HTML) 130 Page - STMicroelectronics

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STR720 - ATAPI-IDE INTERFACE
130/401
12.5.2
IDE Configuration Register Set
Note
Access to the IDE Control Registers is not supported. These registers are used to
control access to the Master interface of the on-chip IDE controller, which is not
supported by this interface.
Note
The Master Latency Timer, bus Master interface address, Ultra DMA Control and
Ultra DMA Timing Registers in the IDE Configuration block should not be used.
These are omitted from the memory map above, flagging their location as reserved.
Addr.
Offset
Register Name
76
5432
10
100h
VENID
(Vendor ID)
Manufacturer’s Identification Number (r)
101h
102h
DEVID
(Device ID)
Device Identification Number (r)
103h
104h
XCMD
(Command)
Reserved
ATAPI Enable
(rw)
105h
Reserved
106h
XSTS
(Status)
Reserved
107h
Reserved
Master Target
Abort Status
(MTAS) (rc)
Receive Target
Abort
(RTA) (rc)
Signaled Target
Abort Status
(STAS) (rc)
Devsel Timing Status
(DEVTS) (r)
Reserved
108h
REVID
(Revision ID)
Revision Identification Number
(r)
109h
(CCP)
Class Code
Programming
Class Code Programming
(r)
10Ah
CCC
(Class Code)
Sub Class 7:0
(r)
10Bh
Base Class 15:8
(r)
10Ch
Reserved
10Dh
10Eh
HTYPE
(Header Type)
Defines format of configuration registers as type 0 and single function
(r)
10Fh
-
13Eh
Reserved
140h
PIDETIM
(Primary IDE
timing)
Drive 1 Timing
Select
(TIM1) (rw)
Drive 1 Enable
Prefetch and
Posting
(PP1EN) (rw)
Drive 1 Enable
IOrdy Sampling
(RDY1EN) (rw)
Drive 1 Fast
Timing Bank
Select
(FTB1) (rw)
Drive 0 Timing
Select
(TIM0) (rw)
Drive 0 Enable
Prefetch and
Posting
(PP0EN) (rw)
Drive 0 Enable
IOrdy Sampling
(RDY0EN) (rw)
Drive 0 Fast
Timing Bank
Select
(FTB0) (rw)
141h
IDE Decode En-
abled
(DCDEN) (rw)
Slave IDE Tim-
ing Enable
(STEN) (rw)
IOrdy Sample Point
(ISPP) (rw)
Reserved
Recovery Time
(RCTP) (rw)
142h
Reserved
143h
144h
SLIDETIM
(Slave IDE
timing)
Reserved
Primary Drive 1 IOrdy Sample
Point
(ISPS) (rw)
Primary Drive 1 Recovery Time
(RCTS) (rw)
1



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