STR720 datasheet(115/401 Pages) STMICROELECTRONICS

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STR720 - EXTERNAL MEMORY INTERFACE (EMI)

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11 EXTERNAL MEMORY INTERFACE (EMI)

11.1 Introduction

The External Memory Interface is a configurable interface designed to control the data flow

from an internal Advanced High-performance Bus (AHB) to external memory components as

ROM and SRAM.

The total external memory space of 8 MByte can be subdivided in 2 regions, corresponding to

the 2 available chip select signals (CS0..CS1). External memory transfers are always 16 bit

wide, the width of the transfers from the AHB bus to the EMI peripheral, in accordance with to

the AHB specifications, are controlled by the HSIZE signal (8,16 or 32-bit). Note that the

external address bus always refers to 16-bit location addresses, thus bit position 0 on this bus

corresponds to bit 1 on the internal AHB address bus.

The length of time required to properly transfer data from/to external memory region is

controlled by programming of internal registers dedicated to each external memory space

which determines the number of wait states used to access that region. Read/Write cycle

termination can be also configured to be controlled by the “External Ready” signal (Eready).

Each internal register also contains a flag bit which informs the controller if a particular

memory space is accessible or not.

All the internal configuration registers are accessed via an Advanced Peripheral Bus interface

(APB) to the EMI block.

11.2 Main Features

■

8 MByte of total addressable external memory space.

■

Up to 2 external regions/chip selects (Banks).

■

Bank 0 can span from 64 kBytes up to 8 MBytes in 64 kBytes increments.

■

Bank 1 can span from 64 kBytes up to 8 MBytes in 64 kBytes increments.

■

Up to 7 configurable wait states for each external memory region.

■

Read/Write cycle termination via “External Ready” (Eready) signal (configurable).

Note

Only chip select 0 signal is always available on STR720 device, CS1 being shared

with different alternate functions or general purpose I/Os.

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