STR720 datasheet(114/401 Pages) STMICROELECTRONICS

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STR720 - DRAM CONTROLLER (DRAMC)

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10.5 Programming considerations

DRAMC programming and usage is accomplished via the internal registers described in

previous paragraphs.

At reset time all the Controller registers will be reset to 0. It is up to the user the correct

programming of the four Bank Size registers and Bank enable bits in the MemConfig register,

in order to properly describe the physical devices connected to the DRAM Controller.

Note that banks are contiguous, even if it is possible to use less than four banks: if an AHB

transfer is accessing a disabled bank, the DRAM Controller will return the error response to

the AHB master (ARM720T CPU or DMA controller).

After power-up the CPU must configure each SDRAM device, i.e. perform the

precharge-refresh-mode register set procedure as specified in the SDRAM device data sheet.

This is accomplished with the correct values in the 8 SDRAMxConfigLo,Hi registers. A write

access to the high registers will start the SDRAM configuration cycle, during which the value

written to the register will be asserted on the memory bus for one clock period.

When ARM720T caches are enabled, all accesses to SDRAM memory are performed as

bursts of 4 transfers and in order to achieve the highest performance level, SDRAM interface

must be aware of this particular access mode. Unfortunately a limitation in ARM720T core

and SDRAM interface requires this specific configuration to be enforced explicitly by software.

This configuration selection is performed by using CACHE_CONFIG bit of SGCR1 register,

which can configure STR720 to work in “burst-access” mode and it should be used whenever

cache is enabled, so to have optimal performance from the system.

In “burst-access” mode all transfers issued by ARM720T core are identified as 16-byte fixed

length burst, possibly early terminated when the actual burst length is shorter than 16, as it

normally happens on cache line refills. In this way any sequence of transfers generated by a

cached ARM720T core fetching its code from a cached region can be legally completed by

SDRAM interface, including multiple register load/store sequences.

When ARM720T is used with its cache disabled or it is fetching its code from a non-cacheable

SDRAM region, this bit should remain cleared, so to avoid incurring in a system hang, when

long sequences of internal instructions generates a sequence of consecutive accesses longer

than a 16-byte burst. In case system hangs for this particular configuration mistake,

application program execution can be restored only with a system reset.

STR720 数据表(PDF) 114 Page - STMicroelectronics