STR720 datasheet(111/401 Pages) STMICROELECTRONICS

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STR720 - DRAM CONTROLLER (DRAMC)

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steps of 16 times the CLK period (TCLK). The REFR value is valid between 0 and

255. For an example of the correspondence between REFR setting and refresh

period see Table 28 Refresh Period..

Size of bank 1 Register (Bank1Size)

Address Offset: 34h

Reset value: 0000h

The Size of bank 1 Register (Bank1Size) is a 16-bit read/write control register used to specify

the size of external region 1 (Bank 1).

The Bank1Size control bits are described below.

Bit 15:9

Reserved (should be written as zero and ignored on read ).

Bit 8:0

SIZE[8:0]: Bank Size.

This field defines the size of the external memory device 1 in 64 kBytes steps.The

SIZE value is valid between 0 and 511, where (SIZE+1) represents the size of the

bank in 64Kbytes steps. See also Table 29 .

Table 28. Refresh Period

REFR

Refresh Period

Refresh period with

fCLK = 48 MHz

00000000

Refresh is disabled

00000001

16 * TCLK

333.33 ns

00000010

32 * TCLK

666.66 ns

00000011

48 * TCLK

µs

...

11111111

4080 * TCLK

µs

6543210

Reserved

SIZE[8:0]

Table 29. Size field and the corresponding actual size

SIZE field

Bank actual size

0.0000.0000

1 x 64kBytes = 64kBytes

0.0000.0001

2 x 64kBytes = 128kBytes

0.0000.0010

3 x 64kBytes = 192kBytes

...

0.0000.1111

16 x 64kBytes = 1MBytes

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