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STR720 数据表(PDF) 147 Page - STMicroelectronics |
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STR720 数据表(HTML) 147 Page - STMicroelectronics |
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147 / 401 page ![]() STR720 - RESET AND CLOCK CONTROL UNIT (RCCU) 147/401 Bit 2 = Reserved. Give ‘0’ when read and must be written to ‘0’. Bit 1 = WDGRST_F: watchdog reset status flag This bit is read only. 0: No Watchdog reset occurred. 1: Watchdog reset occurred. Bit 0 = SWRST_F: software reset status flag This bit is read only. 0: No software reset occurred. 1: Software reset occurred. CLocK ConTroL register (CLKCTL) Address Offset: 0Ch Reset value: 0000h This register is write protected and can be unlocked using REG_PROT bit in SYSPROT register. Bit 15:4 = Reserved. Give ‘0’ when read and must be written to ‘0’. Bit 3 = SWRST: software reset bit 0: No software reset occurs. 1: Software reset occurs. Bit 2 = DIV2: DIV2 select 0: Select CLK as PLLCLKREF 1: Select CLK/2 as PLLCLKREF Bit 1 = IDLE: IDLE mode select bit 0: IDLE mode not selected 1: Select IDLE mode Bit 0 = SLOW: Slow mode select bit 0: SLOW mode not selected 1: Select SLOW mode 15 14 13 12 11 10 9 8 765432 1 0 Reserved SWRS T DIV2 IDLE SLOW -rw rw rw rw 1 |
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