STR720 datasheet(143/401 Pages) STMICROELECTRONICS

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STR720 - RESET AND CLOCK CONTROL UNIT (RCCU)

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13.4 Register description

PLL CONFiguration register (PLLCONF)

Address Offset: 00h

Reset value: 03C7h

This register is write protected and can be unlocked using REG_PROT bit in SYSPROT

Bit 15 = LOCK: PLL locked in

This bit is read only.

0: The PLL is not locked or turned OFF and cannot be selected as system clock source

1: The PLL is locked

Bit 14 = AUTOBYP_EN: auto-bypass enable

This bit enables the auto-bypass mode. In auto-bypass mode when the LOCK bit return to ’0’

the system clock switches back to PLLCLKREF even if the PLLBYP bit is ’0’.

0: auto-bypass mode off

1: auto-bypass mode on

Bit 13:10 = Reserved. Give ‘0’ when read and must be written to ‘0’.

Bit 9 = PLLOFF: PLL switch OFF

0: PLL is switched on

1: PLL is switched off

Bit 8 = PLLBYP: PLL bypass bit (see also AUTOBYP_EN bit)

0: PLL provides the system clock

1: PLL is bypassed and PLLCLKREF is used as system clock

Note

If PLLBYP changes from ‘1’ to ‘0’, but PLLOFF bit is ‘1’, no clock switch occurs since

PLL is switched on again and a stable clock is available, but PLL may be not yet

locked.

Bit 7:6 = DX[1:0]: PLL output clock divider factor.

This bit field selects the divider factor used on the PLL output clock. Refer to Table 36 for PLL

divider setting.

765432

LOCK

AUTOB

YP_EN

Reserved

PLLOFF PLLBYP

DX[1:0]

MX[5:0]

Table 36. PLL divider settings

DX1

DX0

PLLCLKREF/1

PLLCLKREF/2

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